Multi-Channel Transistor Reduces On-Resistance
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Solution Overview
Problem
Current transistor designs face challenges in reducing drain-source on-resistance (RDS(on)) which limits switching speeds and current efficiency, due to various factors including channel region area, diffusion resistance, substrate resistance, and temperature, without increasing transistor size.
Innovation Solution
The design incorporates multiple channel regions arranged in electrical parallel on a silicon-on-insulator (SOI) substrate, with each channel region having the same threshold voltage, allowing for reduced total resistance and increased current flow without increasing the transistor footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the channel region area is increased to reduce drain-source on-resistance, then the transistor size increases, but the device footprint becomes larger
Solution Approach 1:
The transistor channel is divided into multiple discrete channel regions (first channel region, second channel region, third channel region, fourth channel region) arranged in parallel between the source and drain. Each channel region has its own gate electrode, allowing independent control. This segmentation enables the total channel area to be increased while maintaining a compact footprint by utilizing vertical stacking and parallel arrangement rather than horizontal expansion.
Solution Approach 2:
The patent transitions from a planar two-dimensional channel arrangement to a three-dimensional structure with multiple channel regions stacked vertically and arranged in parallel. The channel regions are positioned at different heights and locations, utilizing the third dimension (vertical stacking) to increase total channel area without proportionally increasing the planar footprint. This dimensional transition allows higher channel area density within the same footprint.
2Reliability
If multiple channel regions are added in parallel to reduce resistance, then the transistor complexity increases, but the device structure becomes more complex
Solution Approach 1:
Multiple channel regions are electrically connected in parallel between common source and drain regions. The source regions (first, second, third, fourth source regions) and drain regions (first, second, third, fourth drain regions) are merged to form unified electrical nodes, simplifying the overall connection topology. This merging approach reduces the number of external connections required while maintaining multiple parallel conduction paths, thereby reducing resistance without proportionally increasing complexity.
Solution Approach 2:
The bulk oxide layer serves multiple functions: it acts as an insulator between the semiconductor substrate and the channel regions, provides mechanical support, and enables the formation of multiple discrete channel regions. The gate electrodes collectively control all channel regions, providing universal control functionality. This multi-functionality reduces the need for additional specialized components, thereby managing complexity while achieving resistance reduction.
Data Source
AI summary
In some embodiments, the present disclosure relates to a semiconductor device including a semiconductor region over a bulk oxide, which is over a semiconductor substrate. Above the bulk oxide is a lower source region that is laterally spaced from a lower drain region by a lower portion of the semiconductor region. An upper source region is laterally spaced from an upper drain region by an upper portion of the semiconductor region and is vertically spaced from the lower source region and the lower drain region. The upper source region is coupled to the lower source region, and the upper drain region is coupled to the lower drain region. A gate electrode, coupled to the semiconductor substrate and over a gate oxide, is above the upper portion of the semiconductor region. The lower and upper portions of the semiconductor region respectively include a first channel region and a second channel region.