Host Device Multi-Chip Authentication Chaining to Reduce Interaction Load
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Solution Overview
Problem
Existing authentication methods for multiple chips on a host device require multiple interactions between the host device and each chip, leading to a high load on the host device.
Innovation Solution
A method and device that acquire first authentication data on a communication bus and obtain second authentication data to determine if any of the chips do not meet expectations, reducing interactions by having the host device communicate with only the first and last chips, and using intermediate chips to pass authentication data along the communication bus.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the host device authenticates each chip separately through multiple interactions, then the authentication security is improved, but the load on the host device increases
Solution Approach 1:
The patent introduces intermediate chips as mediators in the authentication process. The first chip receives authentication data from the host device and passes it through intermediate chips to the last chip, which generates the second authentication data. This intermediary structure allows the host device to authenticate multiple chips without directly interacting with each one, thereby reducing host device load while maintaining authentication security through the chained verification process.
2Reliability
If the host device interacts with each chip multiple times for authentication, then the authentication thoroughness is improved, but the information interaction frequency increases
Solution Approach 1:
The patent merges the authentication interactions into a single chained process. Instead of the host device interacting separately with each chip multiple times, the authentication data is passed through a sequence of chips in one continuous flow. The first chip receives initial authentication data, passes it through intermediate chips, and the last chip generates the final authentication result, combining multiple verification steps into a streamlined sequence that reduces total interaction time.
3Measurement precision
If separate authentication is performed for each chip, then the individual chip verification is improved, but the system performance overhead increases
Solution Approach 1:
The patent establishes a continuous authentication flow where data passes seamlessly from the first chip through intermediate chips to the last chip without interruption. This continuous action maintains thorough verification at each stage while eliminating idle periods and redundant operations, thereby improving system performance efficiency. The unbroken chain of authentication ensures each chip is verified individually while the overall process operates efficiently as a unified sequence.
Data Source
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Figure 5A
AI summary
The present disclosure provides a control device, consumables, a host device, and an authentication method, where the control device includes a first acquisition unit, where the first acquisition unit is configured to acquire first authentication data on a communication bus, and the communication bus is configured for communication linkage between the host device and at least two chips; an authentication unit, which obtains second authentication data based on the first authentication data, where the second authentication data is used to determine total authentication data, and the total authentication data is used to determine whether there is a chip, of the at least two chips, that does not meet expectations. In the embodiments of the present disclosure, in the process of authenticating multiple chips, the number of information interactions between the host device and the chips can be reduced, the load of the host device can be reduced, and the system performance overhead can be saved.