Multi-Chip Semiconductor Module With Balanced Gate Switching

Solution Overview

Problem

Existing semiconductor device modules with parallel-connected transistors exhibit inconsistent switching behavior, affecting operating frequencies, electrical efficiency, and signal quality, particularly at higher switching speeds.

Innovation Solution

Implementing electrically balanced signal conduction paths and direct-lead attachments for gate control signals to reduce parasitic impedance, ensuring equal conduction path lengths and balanced connections between transistors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If parallel-connected transistors are used in semiconductor device modules, then power handling capability is improved, but switching consistency deteriorates

Engineering Contradiction:

Improvepower handling capabilityVSAvoidswitching consistency

Core Design Contradiction:

PowerVSReliability

Solution Approach 1:

The patent implements equipotentiality by creating electrically balanced signal conduction paths that ensure equal electrical potential conditions for gate control signals reaching parallel-connected transistors. This is achieved through symmetric routing of signal traces, equalizing the impedance and length of conduction paths from the control signal source to each transistor gate, thereby eliminating potential differences that cause switching inconsistencies.

Inventive Principle:

Principle #12Equipotentiality

Solution Approach 2:

The patent applies parameter changes by systematically adjusting and matching key electrical parameters of the conduction paths, including trace length, trace width, impedance values, and signal propagation delay. By controlling these parameters to be substantially equal across parallel paths, the patent ensures simultaneous switching of parallel-connected transistors while maintaining enhanced power handling capability.

Inventive Principle:

Principle #35Parameter changes

2Use of energy by moving object

If transistor switching speeds are increased, then power efficiency is improved, but switching inconsistency impact worsens

Engineering Contradiction:

Improvepower efficiencyVSAvoidswitching consistency impact

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

The patent implements equipotentiality by creating electrically balanced signal conduction paths that ensure equal electrical potential conditions for gate control signals reaching parallel-connected transistors. This is achieved through symmetric routing of signal traces, equalizing the impedance and length of conduction paths from the control signal source to each transistor gate, thereby eliminating potential differences that cause switching inconsistencies.

Inventive Principle:

Principle #12Equipotentiality

Solution Approach 2:

The patent applies parameter changes by systematically adjusting and matching key electrical parameters of the conduction paths, including trace length, trace width, impedance values, and signal propagation delay. By controlling these parameters to be substantially equal across parallel paths, the patent ensures simultaneous switching of parallel-connected transistors while maintaining enhanced power handling capability.

Inventive Principle:

Principle #35Parameter changes

3Reliability

If electrical connections to transistor terminals are made, then electrical functionality is achieved, but parasitic impedance varies causing switching imbalance

Engineering Contradiction:

Improveelectrical functionalityVSAvoidparasitic impedance variation

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies parameter changes by systematically adjusting and matching key electrical parameters of the conduction paths, including trace length, trace width, impedance values, and signal propagation delay. By controlling these parameters to be substantially equal across parallel paths, the patent ensures simultaneous switching of parallel-connected transistors while maintaining enhanced power handling capability.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent converts the harmful effect of parasitic impedance by designing the conduction paths to have controlled and matched impedance characteristics. Rather than attempting to eliminate parasitic impedance entirely, the patent accepts its presence but ensures that the impedance parameters are equalized across parallel paths, thereby converting the potential harm into a controlled parameter that maintains switching consistency.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Data Source

PatentUS20250279340A1Multi-chip semiconductor module with balanced switching

Publication Date: 2025.09.04 SEMICON COMPONENTS IND LLC

AI summary

In a general aspect, a semiconductor device assembly includes a substrate having a patterned metal layer disposed thereon, a first semiconductor die, the first semiconductor die disposed on a first portion of the patterned metal layer, and a second semiconductor die disposed on the first portion of the patterned metal layer. The assembly also includes a first electrical connection electrically coupling a second portion of the patterned metal layer with the first semiconductor die. and a second electrical connection electrically coupling the second portion of the patterned metal layer with the second semiconductor die. The second electrical connection is substantially electrically balanced with the first electrical connection.