Multi-Chip Bump Structures for Heterogeneous Packaging
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Solution Overview
Problem
Current chip packaging technologies face challenges in bonding chips with different bump sizes on a single substrate, as the manufacturing process becomes more complicated and expensive with increasing numbers of different sized bumps, and not all manufacturers have the capability to produce smaller micro-bumps required for advanced packaging.
Innovation Solution
The solution involves forming bump structures by aligning and bonding larger bumps on chips with multiple smaller micro-bumps on a substrate, where the smaller bumps share the burden of carrying current and provide a stronger connection, allowing chips with varying bump sizes to be packaged together by reflowing solder between aligned bumps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple different sized bumps are used on a substrate to accommodate chips with varying bump sizes, then the adaptability of the packaging system is improved, but the device complexity and manufacturing cost increase
Solution Approach 1:
The invention divides a single large bump into multiple smaller micro-bumps (e.g., four 20-micron micro-bumps instead of one 40-micron bump). This segmentation allows the substrate to use uniform small micro-bumps for all chip connections, while chips with different bump sizes can be accommodated by matching their bumps to appropriate groups of micro-bumps. The segmentation resolves the contradiction by enabling adaptability through standardized small units rather than requiring multiple different sized bump types.
Solution Approach 2:
Instead of making the substrate accommodate different sized bumps directly (which increases complexity), the invention inverts the approach by having the substrate use only small micro-bumps and allowing larger chip bumps to connect to multiple micro-bumps simultaneously. This inversion simplifies the substrate manufacturing while maintaining the ability to package chips with varying bump sizes.
2Productivity
If smaller micro-bumps are used to increase connection density, then the productivity and electrical connection capability are improved, but the manufacturing capability requirements increase
Solution Approach 1:
The invention combines multiple small micro-bumps into a single bonding unit that connects to one larger chip bump. For example, four 20-micron micro-bumps are bonded together to form a single connection point that interfaces with a 40-micron chip bump. This merging approach enables high connection density and electrical capability through multiple parallel connections, while the manufacturing process remains feasible because the micro-bumps are formed using standard semiconductor fabrication processes.
3Ease of manufacture
If larger bumps are used on chips, then the ease of manufacture is improved, but the connection strength and current carrying capacity are reduced
Solution Approach 1:
The invention transitions from a single-dimension connection (one large bump to one large bump) to a multi-dimensional connection where multiple small micro-bumps connect to one large chip bump. This dimensional change allows the connection strength and current carrying capacity to be increased through parallel multiple connections, while the chip manufacturing remains easy because it uses the chip's existing large bump structure without requiring modification.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the efficient packaging of chips with different bump sizes on a common substrate, reducing manufacturing complexity and cost, while ensuring reliable electrical connections, thereby improving the package form factor and functionality of multi-chip devices.
Implementation Method 1
reflowing solder between aligned bumps
Implementation Method 2
reflowing solder between aligned bumps
Data Source
AI summary
A multi-chip package includes a substrate having a plurality of first bump structures. A pitch between first bump structures of the plurality of first bump structures is uniform across a surface of the substrate. The multi-chip package includes a first chip bonded to the substrate and a second chip bonded to the substrate. The first chip includes a plurality of second bump structures, and the plurality of second bump structures are bonded to a first set of first bump structures of the plurality of first bump structures. The second chip includes a plurality of third bump structures, and the plurality of third bump structures are bonded to a second set of first bump structures of the plurality of first bump structures. A pitch between second bump structures of the plurality of second bump structures is different from a pitch between third bump structures of the plurality of third bump structures.


