Multi-Chip Nonvolatile Memory Clock Duty Training Without Longer Setup
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Solution Overview
Problem
Conventional nonvolatile memory devices face performance degradation due to duty mismatch in clock signals, leading to reduced effective data windows and increased DCC training periods, especially as the number of memory chips increases, which affects communication efficiency between nonvolatile memory and controllers.
Innovation Solution
Incorporating a duty correction circuit (DCC) in each memory chip to perform parallel duty correction operations during a dedicated training period, using external clock signals to generate buffered internal clock signals, and employing output buffers to transmit corrected signals, thereby maintaining constant DCC training periods regardless of the number of memory chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory chips are used to increase storage capacity, then the storage capacity is improved, but the duty mismatch in clock signals worsens leading to reduced effective data windows
Solution Approach 1:
The patent divides the memory system into multiple independent memory chips, each with its own duty correction circuit. This segmentation allows each chip to independently correct its clock signal duty cycle, preventing the accumulation of duty mismatch errors that would occur in a monolithic system, thereby maintaining reliable effective data windows despite increased storage capacity.
Solution Approach 2:
The duty correction circuit acts as an intermediary between the external clock signal and the internal logic circuits. It receives the external clock signal, corrects its duty cycle to match the internal reference clock, and provides the corrected signal to subsequent stages, thus eliminating duty mismatch issues in multi-chip configurations.
2Measurement precision
If duty correction operations are performed sequentially in multiple memory chips, then the duty correction accuracy is improved, but the training period duration increases
Solution Approach 1:
The patent merges the duty correction operations of multiple memory chips by enabling them to operate in parallel during the training period. Each chip's duty correction circuit simultaneously adjusts its clock signal based on the same external reference, achieving both high accuracy and time efficiency by combining multiple correction processes rather than executing them sequentially.
Solution Approach 2:
The duty correction circuits are designed to perform preliminary adjustment of clock signals during the training period before normal operation begins. This preliminary action establishes the correct duty cycle relationship between external and internal clocks, ensuring accurate timing is set before data transfer operations start, thereby maintaining both accuracy and minimizing training time.
3Measurement precision
If duty correction circuits are added to each memory chip to correct clock signals, then the duty cycle accuracy is improved, but the device complexity increases
Solution Approach 1:
The patent applies local quality by implementing duty correction functionality only where needed - specifically in each memory chip that requires precise clock timing. Rather than adding complex global synchronization mechanisms to the entire system, each chip independently possesses the necessary correction capability, localizing the complexity to only the components that require it, thus achieving high duty cycle accuracy without excessive overall system complexity.
Data Source
AI summary
Provided is a nonvolatile memory including a clock pin configured to receive an external clock signal during a duty correction circuit training period; a plurality of memory chips configured to perform a duty correction operation on an internal clock signal based on the external clock signal, the plurality of memory chips configured to perform the duty correction operation in parallel during the training period; and an input/output pin commonly connected to the plurality of memory chips, wherein each of the plurality of memory chips includes: a duty correction circuit (DCC) configured to perform the duty correction operation on the internal clock signal; and an output buffer connected between an output terminal of the DCC and the input/output pin.