Multi-Chip Counter Synchronization Using a Single Control Line
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Solution Overview
Problem
Conventional synchronous processing systems for semiconductor integrated circuits lack efficient start and stop control mechanisms, requiring additional terminals and control circuits for external signal management.
Innovation Solution
A synchronous processing system where each semiconductor integrated circuit has a counter that synchronizes with a master chip's clock pulses using a synchronization control signal, allowing simultaneous start and stop of processing operations and correcting synchronization deviations through a single synchronization control line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If start/stop control is performed via external signal in conventional synchronous processing systems, then processing operations can be controlled, but additional terminals and control circuits are required
Solution Approach 1:
The synchronization control signal line is designed to serve multiple functions: it synchronizes clock pulses between master and slave chips, and simultaneously conveys start/stop control instructions. This multi-functionality eliminates the need for separate control terminals and circuits, resolving the contradiction between operational control capability and device complexity
Solution Approach 2:
The patent merges the synchronization function and control function into a single synchronization control signal line. The master chip combines synchronization signal generation with control signal generation, while slave chips combine synchronization reception with control signal reception, thereby reducing the number of required terminals and control circuits
2Productivity
If multiple chips operate independently without synchronized counter control, then each chip has operational independence, but synchronization deviation accumulates and processing coordination fails
Solution Approach 1:
The master chip generates synchronization control signals based on its counter reaching a predetermined value, creating a feedback mechanism. This feedback ensures that all slave chips reset and resynchronize their counters simultaneously with the master chip, preventing synchronization deviation accumulation and maintaining stable multi-chip operation
Solution Approach 2:
The synchronization control signal is generated periodically each time the master chip's counter reaches the predetermined value. This periodic action ensures continuous synchronization of all slave chip counters with the master chip, maintaining stable synchronization throughout operation
Data Source
AI summary
A synchronous processing system having semiconductor integrated circuits. One of the semiconductor integrated circuits as a master chip includes a first synchronization controller and a first counter controller that allows a counter in the master chip to perform counting synchronously with a clock pulse in response to a synchronization control signal from the first synchronization controller. Another semiconductor integrated circuit as a slave chip includes a second synchronization controller that receives the synchronization control signal from the master chip, and a second counter controller that allows a counter in the stave chip to perform counting synchronously with the clock pulse in response to the synchronization control signal received. Each of the first and second counter controllers allows the counter to stop counting if the synchronization control signal is not supplied at the time point that a count value of the counter has reached a predetermined value.