Multi-Chip FPGA Logic Drive With NVM to Cut ASIC NRE
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Solution Overview
Problem
The current Field Programmable Gate Array (FPGA) IC chips have limitations such as larger size, lower yield, higher fabrication cost, higher power consumption, and lower performance compared to Application Specific IC (ASIC) or Customer-Owned Tooling (COT) chips. Additionally, the high Non-Recurring Engineering (NRE) cost for designing ASIC or COT chips using advanced technology nodes slows down innovation and increases barriers for implementing new semiconductor technologies.
Innovation Solution
A standardized commodity logic drive is introduced, comprising multiple FPGA IC chips and one or more non-volatile memory IC chips. This approach allows for field programming to meet different application requirements, reducing the need for expensive ASIC or COT chip design and production. The logic drive is designed to be cost-effective and efficient, using advanced semiconductor technology nodes while minimizing NRE costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FPGA IC chips are used for application development, then adaptability and ease of operation are improved, but chip size increases, fabrication cost increases, power consumption increases, and performance decreases
Solution Approach 1:
The system is divided into multiple segments: commodity FPGA chips for logic functions, non-volatile memory chips for configuration storage, and controller chips for coordination. This segmentation allows each component to be optimized independently, reducing the overall footprint while maintaining adaptability.
Solution Approach 2:
The patent creates a universal platform using standardized commodity FPGA chips that can be configured for different applications through software loading. This multi-functional approach eliminates the need for application-specific custom chips, reducing chip size and fabrication costs while maintaining versatility across multiple use cases.
2Adaptability or versatility
If FPGA IC chips are used for application development, then adaptability is improved, but fabrication cost increases
Solution Approach 1:
The patent employs inexpensive commodity FPGA chips that can be mass-produced using standard fabrication processes. These off-the-shelf components replace expensive custom ASICs, significantly reducing fabrication costs while maintaining reconfigurability through software-based configuration loading.
Solution Approach 2:
The system changes the state of FPGA configuration from hardware-coded (in custom chips) to software-loaded (from non-volatile memory). This parameter change enables the use of commodity components with standard fabrication processes, reducing manufacturing costs while preserving adaptability through programmable configuration.
3Adaptability or versatility
If FPGA IC chips are used for application development, then adaptability is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic configuration where FPGA logic is loaded and activated only when needed, rather than being permanently instantiated. This dynamic approach allows the system to power down unused logic functions, reducing overall power consumption while maintaining adaptability for future configuration changes.
4Productivity
If ASIC or COT IC chips are used for advanced technology nodes, then performance is improved, but NRE cost increases greatly
Solution Approach 1:
The patent uses commodity FPGA chips as copies or approximations of custom ASIC functionality. By loading configuration bitstreams from non-volatile memory, these standard chips replicate the desired logic functions without requiring expensive custom mask sets, achieving performance adequate for many applications at a fraction of the NRE cost.
Solution Approach 2:
The system creates a universal computing platform using commodity components that can be configured for different applications. This multi-functional approach replaces the need for multiple application-specific custom chips, each requiring expensive NRE investment, with a single reconfigurable platform that achieves comparable performance across diverse workloads.
5Ease of manufacture
If commodity FPGA IC chips are used, then NRE cost is reduced, but chip size and performance are limited
Solution Approach 1:
The patent merges multiple commodity FPGA chips into a multi-chip module package, combining their computational resources to achieve performance levels comparable to or exceeding custom ASICs. This parallel processing approach leverages the aggregate power of multiple standard chips to overcome the performance limitations of individual commodity devices.
Data Source
AI summary
A chip package used as a logic drive, includes: multiple semiconductor chips, a polymer layer horizontally between the semiconductor chips; multiple metal layers over the semiconductor chips and polymer layer, wherein the metal layers are connected to the semiconductor chips and extend across edges of the semiconductor chips, wherein one of the metal layers has a thickness between 0.5 and 5 micrometers and a trace width between 0.5 and 5 micrometers; multiple dielectric layers each between neighboring two of the metal layers and over the semiconductor chips and polymer layer, wherein the dielectric layers extend across the edges of the semiconductor chips, wherein one of the dielectric layers has a thickness between 0.5 and 5 micrometers; and multiple metal bumps on a top one of the metal layers, wherein one of the semiconductor chips is a FPGA IC chip, and another one of the semiconductor chips is a NVMIC chip.