Multi-Chip Gate Redistribution for Synchronized Power Switching
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Solution Overview
Problem
Conventional power transistor device packages using ceramic-based carriers for chip wiring are expensive and require high performance, which is not met by cheaper alternatives, and the use of multiple chips with different wire bond lengths leads to inconsistent switch-on times.
Innovation Solution
A power device package design with parallelized power transistor chips connected via wire bonds of varying lengths and cross-sectional areas to match bond performance, ensuring synchronized switch-on behavior and reduced manufacturing costs by using cheaper components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ceramic-based carriers are used for chip wiring, then insulation performance and design flexibility are improved, but manufacturing cost increases
Solution Approach 1:
The patent uses wire bond connections as a substitute for the complex ceramic carrier wiring system. By creating simplified electrical connections that replicate only the essential functionality, the design achieves adequate performance without the expensive ceramic substrate, directly resolving the cost-performance contradiction
Solution Approach 2:
The patent replaces the expensive, high-performance ceramic carrier with cheaper wire bond connections. This substitution uses lower-cost components to achieve the necessary electrical insulation and connectivity, eliminating the need for costly ceramic-based carriers while maintaining functional requirements
2Adaptability or versatility
If wire bond connections of different lengths are used, then connection flexibility is improved, but switch-on time consistency deteriorates
Solution Approach 1:
The patent applies different cross-sectional areas to wire bonds based on their specific functional requirements. By optimizing the local properties (wire thickness) of each connection, the design achieves both the needed connection flexibility and consistent electrical performance, resolving the contradiction between adaptability and precision
Solution Approach 2:
The patent compensates for variations in wire bond length by adjusting the cross-sectional area parameter. This parameter change allows longer wires to maintain the same inductance characteristics as shorter wires, ensuring consistent switch-on times across all power transistor chips while preserving connection flexibility
3Power
If multiple power transistor chips are parallelized, then power density is improved, but switch-on time synchronization deteriorates
Solution Approach 1:
The patent optimizes each wire bond connection individually by adjusting its cross-sectional area according to its specific length and electrical requirements. This localized optimization ensures that all parallelized power transistor chips receive gate signals with matched inductance characteristics, achieving synchronized switch-on behavior while maintaining high power density through multi-chip parallelization
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves synchronized switch-on behavior across multiple chips, reducing manufacturing costs while maintaining high performance, and allows for scalable and efficient power device packages.
Implementation Method 1
a control package terminal electrically coupled to a control electrode of the first power transistor chip via a first wire bond connection and to a control electrode of the second power transistor chip via a second wire bond connection
Data Source
AI summary
A power device package includes first and second power transistor chips each having a control electrode, a first load electrode and a second load electrode. A control package terminal is electrically coupled to the control electrode of the first power transistor chip via a first wire bond connection and to the control electrode of the second power transistor chip via a second wire bond connection. A first package terminal is electrically coupled to the first load electrode of the first and second power transistor chips. A second package terminal is electrically coupled to the second load electrode of the first power transistor chip and/or the second power transistor chip. A length of the first wire bond connection is greater than a length of the second wire bond connection, and a cross-sectional area of the first wire bond connection is greater than a cross-sectional area of the second wire bond connection.