Multi-Chip GPU Partitioning for Fair QoS and Data Isolation
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Solution Overview
Problem
Existing graphics processing units (GPUs) face challenges in efficiently partitioning hardware resources among virtual machines while ensuring fair resource allocation and data isolation for security purposes, particularly in cloud computing environments where customers rent partial hardware resources.
Innovation Solution
Implementing a multi-chip GPU architecture with chiplet isolation and quality of service (QoS) mechanisms to compartmentalize compute partitions, ensuring each partition receives its fair share of resources and maintains data isolation through encryption and dedicated memory paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If hardware resources are partitioned among virtual machines, then resource utilization efficiency is improved, but data isolation and security between partitions deteriorates
Solution Approach 1:
The patent divides the GPU into multiple chiplets, each capable of being independently assigned to different virtual machines. This segmentation allows fine-grained resource partitioning while maintaining isolation boundaries through separate memory controllers and inter-chiplet communication paths, resolving the contradiction between efficient resource sharing and data isolation.
Solution Approach 2:
The patent introduces a memory controller as an intermediary component between chiplets and memory. This intermediary manages isolation by controlling memory access paths and implementing security measures such as encryption for data transferred between partitions, enabling secure resource sharing.
2Reliability
If chiplet isolation is implemented, then data security and fault isolation are improved, but device complexity increases
Solution Approach 1:
The patent designs chiplets with universal interfaces and standardized communication protocols that can work across different configurations. The same chiplet can be assigned to different virtual machines with different workload requirements, reducing the need for custom isolation mechanisms for each scenario and simplifying the overall architecture.
Solution Approach 2:
The patent implements nested isolation layers where chiplet-level isolation is combined with virtual machine-level virtualization. The memory controller provides hardware-level isolation, while software virtualization adds additional isolation layers, creating a nested structure that manages complexity through hierarchical organization.
3Reliability
If dedicated memory paths are created for each partition, then resource allocation fairness is improved, but device complexity and bandwidth consumption increase
Solution Approach 1:
The patent implements dynamic memory path allocation where memory controllers can be reassigned to different chiplets based on current workload demands. This dynamic configuration allows the system to provide fair resource allocation without committing to fixed dedicated paths, reducing complexity while maintaining fairness through flexible, demand-based resource distribution.
Data Source
AI summary
One embodiment provides a graphics processor comprising a system interface and a plurality of chiplets coupled with the system interface. Each of the plurality of chiplets is configurable to be assigned to a partition of a plurality of partitions. A chiplet of the plurality of chiplets includes an interface to a memory device, a cache memory coupled with the interface to the memory device, and a graphics core cluster coupled with the interface to the memory device and the cache memory, the graphics core cluster including a plurality of graphics cores configured to execute graphics and compute workloads.