Multi-Chip IC Positioning Using Dual Reference Markers
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Solution Overview
Problem
In multi-chip packages, accurately positioning integrated circuits (ICs) relative to each other and an underlying substrate is challenging, leading to issues like interconnects crossing or shorting, which can result in inoperable and unreliable packaged IC chips.
Innovation Solution
The use of a substrate package with a first set of reference markers for initial alignment and a second set of reference markers for confirmation, disposed at different locations, to ensure accurate positioning of multiple ICs, including a method for positioning and confirming the alignment of ICs in multi-chip packaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a single set of reference markers is used for IC positioning, then the device complexity is reduced, but the manufacturing precision deteriorates due to inability to confirm alignment accuracy
Solution Approach 1:
The reference marker system is segmented into two distinct sets: a first set used for initial IC positioning and a second set used for alignment confirmation. This segmentation allows the positioning process to be divided into two stages, where the first set establishes the primary alignment and the second set verifies the accuracy, thereby improving manufacturing precision without requiring a single complex marker system
Solution Approach 2:
The second set of reference markers acts as an intermediary verification mechanism between the positioning action and the final alignment assessment. By introducing this intermediate confirmation step, the system ensures that IC positioning accuracy is validated independently, resolving the contradiction between simplicity and precision
2Reliability
If reference markers are placed at a single location, then the device complexity is reduced, but the reliability deteriorates due to insufficient alignment confirmation
Solution Approach 1:
The reference marker system is spatially segmented into two locations: a first location containing markers for initial positioning and a second location containing markers for alignment confirmation. This spatial segmentation ensures that alignment verification is performed from multiple positions, improving reliability by preventing localized errors while maintaining manageable device complexity through modular marker placement
Solution Approach 2:
The second set of reference markers provides feedback on the accuracy of the positioning performed using the first set. This feedback mechanism allows for verification and potential correction of alignment errors, thereby improving reliability by ensuring that the IC is correctly positioned before final packaging
Data Source
AI summary
Embodiments of the present invention include a method for multi-chip packaging. For example, the method includes positioning a first integrated circuit (IC) on a substrate package based on a first set of reference markers in physical contact with the substrate package and confirming an alignment of the first IC based on a second set of reference markers in physical contact with the substrate package. A second IC is stacked onto first IC based on the first set of reference markers. An alignment of the second IC is confirmed based on the second set of reference markers, where the second set of reference markers is disposed at a different location on the substrate package than the first set of reference markers.