3D Stacked Multi-Chip Imaging Package
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Solution Overview
Problem
Conventional imaging systems with single-die designs face challenges in achieving compactness due to the substantial space required for control and processing circuitry, making it difficult to design high-density image sensor arrays and circuitry within a constrained area, especially in devices like cellular telephones and cameras.
Innovation Solution
The implementation of a multi-chip package configuration where an image sensor chip is stacked on top of an image signal processing chip, using a semiconductor package substrate with wire bonding and an adhesive layer to facilitate signal exchange, and a cover glass to protect the image sensor, allowing for efficient use of space and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If control and processing circuitry are formed laterally from image sensor pixels on a single silicon substrate, then integration is achieved, but the lateral footprint of the image sensor chip increases substantially
Solution Approach 1:
The patent transitions from a planar (2D) single-die architecture to a three-dimensional (3D) stacked multi-chip architecture. The image sensor array and control/processing circuitry are separated onto different chips stacked vertically, with the first chip containing the image sensor array and the second chip containing the control and processing circuitry, connected through vertical interconnects. This dimensional change allows high integration without increasing lateral footprint.
2Ease of manufacture
If a single-die design is used to integrate image sensor pixels and control circuitry, then manufacturing is simplified, but the device size increases making it unsuitable for compact imaging systems
Solution Approach 1:
The patent divides the previously monolithic single-die design into multiple separate chips: a first chip containing the image sensor array and a second chip containing the control and processing circuitry. Each chip can be manufactured using optimized processes for its specific function, then stacked and interconnected. This segmentation enables compact 3D integration while maintaining manufacturing feasibility through specialized processes for each chip type.
3Productivity
If more integrated circuit real estate is allocated to control and processing circuitry, then processing capability is improved, but the lateral footprint increases which is undesirable for compact systems
Solution Approach 1:
The patent resolves this contradiction by moving the control and processing circuitry from the lateral plane to the vertical dimension through chip stacking. The second chip in the stack contains the control and processing circuitry, connected to the image sensor array on the first chip through vertical interconnects. This allows substantial processing capability to be integrated without increasing the lateral footprint, as the additional circuitry occupies vertical space rather than horizontal space.
Data Source
AI summary
A multi-chip package may include an image sensor chip, an image signal processor (ISP) chip, a cover glass, and a package substrate. The ISP chip may be placed on the substrate. The image sensor chip may be placed over the ISP chip. An adhesive film may be formed between the ISP and image sensor chips. A cover glass may be suspended above the image sensor chip. The ISP chip and the image sensor chip may be wire bonded to the substrate. The multi-chip package may be hermetically sealed using a liquid compound or a dam structure. During normal operation, the ISP chip sends control signals to the image sensor chip via a first set of wire bond members and conductive traces in the substrate while the image sensor chip sends output signals to the ISP chip via a second set of wire bond terminals and conductive traces in the substrate.