Multi-Chip Lead Frame Layout for Double-Sided Semiconductor Cooling
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Solution Overview
Problem
Power semiconductor devices face challenges with heat dissipation, leading to thermal management issues and increased electrical resistance, which can affect their performance and lifespan, especially in high-power applications. Additionally, existing manufacturing processes are complex and costly, requiring simplification to improve productivity and yield.
Innovation Solution
A semiconductor device design featuring a substrate with multiple semiconductor chips and a lead frame structure that includes groove and bending regions, allowing for double-sided heat dissipation and reduced electrical resistance, while simplifying the manufacturing process through optimized heat sink placement and material usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If single-side cooling method is used, then device structure is simple, but heat dissipation capability is limited and thermal resistance is high
Solution Approach 1:
The patent transitions from single-side cooling to double-sided cooling by adding heat dissipation functionality in another dimension (the opposite side of the module). This allows heat to be dissipated from both upper and lower surfaces, effectively doubling the heat dissipation area and improving thermal performance without proportionally increasing structural complexity.
Solution Approach 2:
The lead frame is segmented into multiple functional regions including first groove region, second groove region, first bending region, and second bending region. This segmentation allows independent optimization of each region for its specific function (electrical connection, heat dissipation, mechanical flexibility) while maintaining overall structural integrity.
2Strength
If lead frame is made thicker to improve mechanical strength, then structural integrity is improved, but electrical resistance increases
Solution Approach 1:
The lead frame employs different thicknesses in different regions: thicker in areas requiring mechanical strength (such as regions connecting to semiconductor chips) and thinner in areas where electrical conductivity is prioritized. This local quality variation allows simultaneous optimization of both mechanical strength and electrical conductivity without compromising either property.
3Productivity
If manufacturing process is simplified, then productivity increases and cost decreases, but manufacturing precision may be affected
Solution Approach 1:
The patent combines multiple functions into integrated structures: the lead frame simultaneously provides electrical connection, heat dissipation, and mechanical support functions. The groove regions and bending regions are integrated into the lead frame itself rather than being separate components, reducing the number of manufacturing steps while maintaining precise geometric requirements through single-piece forming processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enhances heat dissipation, improves thermal resistance characteristics, reduces electrical resistance, and simplifies the manufacturing process, leading to increased productivity and cost-effectiveness.
Implementation Method 1
a heat sink formed at a position corresponding to the first semiconductor chip and the second semiconductor chip on the first lead frame
Implementation Method 2
the heat sink may include: a lower metal layer connected to an upper surface of the first lead frame; an insulating layer formed on the lower metal layer
Data Source
AI summary
Provided is a semiconductor device. A semiconductor device may include: a substrate formed to extend along a first direction; a first semiconductor chip formed on the substrate; a second semiconductor chip formed on the substrate at a predetermined distance from the first semiconductor chip along the first direction; a first lead frame extending outwardly beyond the substrate along the first direction, the first lead frame having a lower surface connected to upper surfaces of each of the first semiconductor chip and the second semiconductor chip; and a heat sink formed at a position corresponding to the first semiconductor chip and the second semiconductor chip on the first lead frame, wherein the first lead frame includes a first groove region formed between a region on the lower surface connected to the upper surface of the first semiconductor chip and a region on the lower surface connected to the upper surface of the second semiconductor chip.