Multi-chip Leadless Module Parasitic Reduction
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Solution Overview
Problem
Conventional multi-chip modules for battery protection circuits are large due to numerous external leads and wire bonds, which increase parasitic inductance, resistance, and capacitance, limiting their current carrying capacity and efficiency.
Innovation Solution
A multi-chip leadless module with dual n-channel MOSFETs sharing a common drain, assembled using flip chip technology without wire bonds, where the MOSFETs and control IC are mounted face down on a leadframe with exposed contacts, reducing the module's footprint and parasitic effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonds are used to connect MOSFETs and IC, then electrical connections can be established, but parasitic inductance, resistance and capacitance increase adversely impacting performance
Solution Approach 1:
The patent removes wire bonds from the module architecture entirely. Instead of using wire bonds to connect the MOSFETs and control IC to the leadframe, the devices are directly mounted face-down on the leadframe with their contact surfaces making direct contact with the leadframe contact surfaces. This extraction of the wire bond element eliminates the parasitic inductance, resistance and capacitance that wire bonds introduce.
Solution Approach 2:
The patent replaces the wire bond mechanical connection system with a direct surface-mount mechanical system. The MOSFETs and control IC are mounted face-down on the leadframe such that their contact surfaces directly contact the leadframe contact surfaces, substituting the wire bond mechanical assembly with a direct mechanical and electrical contact interface that eliminates parasitic effects.
2Adaptability or versatility
If conventional multi-chip module design with leads on all four sides is used, then all connections can be made, but module size increases which is undesirable for small electronic devices
Solution Approach 1:
The patent transitions from a planar two-dimensional layout with leads on all four sides to a three-dimensional stacked architecture where devices are mounted face-down on the leadframe. This dimensional change allows connections to be made through vertical stacking rather than horizontal spreading, reducing the module footprint while maintaining full connection capability between the control IC, MOSFETs, and external leads.
Solution Approach 2:
The patent merges the electrical connection function with the mechanical support function by integrating the leadframe to serve both as the structural skeleton and as the electrical interconnection medium. The leadframe contact surfaces directly contact the device contact surfaces, combining mechanical mounting and electrical connection into a single integrated structure, eliminating the need for separate wire bonds and reducing overall module size.
3Area of stationary object
If power MOSFET size is reduced to fit smaller packages, then module size decreases, but current carrying capacity is reduced
Solution Approach 1:
The patent uses vertical stacking in the third dimension to accommodate larger power MOSFET devices within a compact footprint. By mounting the MOSFETs face-down on the leadframe and utilizing the vertical space for heat sinks and connections, the design allows larger current-capable devices to be integrated without increasing the horizontal module dimensions.
Solution Approach 2:
The leadframe serves as an intermediary that directly contacts the contact surfaces of the power MOSFETs, providing low-resistance electrical pathways for high current. This direct contact interface, combined with integrated heat sinks attached to the MOSFET back surfaces, enables the MOSFETs to dissipate heat efficiently and carry higher currents without overheating, maintaining power capability in a compact form factor.
Data Source
AI summary
The multi-chip leadless module 200 has integrated circuit (IC) 150, dual n-channel mosfet 110, IC leads 210, 211, 212, gate leads 213, 213, and source leads 217-220 encapsulated in resin 250. The IC 150 and the dual n-channel mosfet 110 are mounted face down on the leads. IC leads 210, 211, 212 are made of planar metal and connect, respectively, to the electrodes TEST, VDD and VM on the IC 150 using a flip chip technique to assemble the leads on copper pillars or copper studs.