Multi-chip LED with Resin Buffer for Thermal Stress Relief

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Solution Overview

Problem

The difference in thermal expansion coefficients between semiconductor light emitting devices and mounting substrates leads to stress on the semiconductor layer, potentially causing cracking due to the mismatch in thermal expansion, which existing technologies fail to adequately address.

Innovation Solution

The semiconductor light emitting device employs a multi-chip structure with a convex-concave shape and an insulating layer to distribute stress, using metal pillars and a flexible resin layer to absorb and relax stress, while maintaining a broad light emitting region and enhancing mechanical strength.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a semiconductor light emitting device is flip-chip mounted on a mounting substrate, then electrical connection and mounting stability are improved, but stress concentration on the semiconductor layer occurs due to thermal expansion coefficient mismatch

Engineering Contradiction:
Improvemounting stabilityVSAvoidstress on semiconductor layer
Core Design Contradiction:
ReliabilityVSStress or pressure

Solution Approach 1:

The patent divides the semiconductor layer into multiple chips arranged in an array, with each chip having independent p-side and n-side external terminals. This segmentation allows stress to be distributed across multiple smaller units rather than concentrated on a single large chip, reducing the overall stress impact on the semiconductor layer while maintaining electrical connection stability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a resin layer as an intermediary substance between the semiconductor chips and the mounting substrate. This resin layer has a thermal expansion coefficient that matches both the semiconductor layer and the mounting substrate, acting as a buffer that absorbs thermal expansion mismatches and reduces stress transmission to the semiconductor chips during temperature changes.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Illumination intensity

If the semiconductor layer is made larger to increase light output, then luminous intensity is improved, but the device becomes more susceptible to cracking due to stress

Engineering Contradiction:
Improvelight outputVSAvoidresistance to cracking
Core Design Contradiction:
Illumination intensityVSStrength

Solution Approach 1:

The patent achieves high light output not through a single large semiconductor layer but by arranging multiple smaller chips in an array configuration. Each chip emits light independently, and the combined output of all chips provides high overall luminous intensity. This segmentation approach maintains the total light output while making each individual chip more resistant to stress-induced cracking.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the structural parameter of the semiconductor layer from a single large continuous layer to multiple discrete chips with specific spacing and arrangement. This parameter change allows the system to maintain high total light emitting area while reducing the stress concentration risk in each individual chip, as smaller chips have lower absolute stress accumulation.

Inventive Principle:
Principle #35Parameter changes

3Illumination intensity

If multiple chips are used to increase light output, then illumination intensity is improved, but device complexity increases

Engineering Contradiction:
Improvelight outputVSAvoidmulti-chip structure
Core Design Contradiction:
Illumination intensityVSDevice complexity

Solution Approach 1:

The patent designs each chip with both p-side and n-side external terminals that can serve multiple functions. The external terminals not only provide electrical connection for current injection but also serve as heat dissipation paths and mechanical attachment points. This multi-functionality reduces the need for additional separate components, thereby managing device complexity despite using multiple chips.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the functions of multiple chips into a single integrated array structure mounted on a common substrate. The chips are arranged in a compact configuration where they share common mounting infrastructure, wiring routes, and heat dissipation pathways. This merging approach allows multiple chips to work together as a unified device, achieving high light output without proportionally increasing overall device complexity.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively reduces stress concentration on the semiconductor layer, preventing cracking and improving the reliability and heat dissipation of the device, while maintaining high light output and mechanical stability.

Implementation Method 1

due to the difference in thermal expansion coefficients between a semiconductor layer and the mounting substrate, the influence of stress on the semiconductor layer is a concern

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Implementation Method 2

the resin layer has a rigidity lower than the rigidity of the semiconductor layer. Accordingly, it is possible to relax stress added to the semiconductor layer

Methodology Applied
Scientific EffectStress relaxation: Stress Relaxation

Data Source

PatentUS9171882B2Semiconductor light emitting device and light emitting module
Publication Date: 2015.10.27 SEOUL SEMICONDUCTOR
  • US9171882B2 patent drawing
  • US9171882B2 patent drawing
  • US9171882B2 patent drawing

AI summary

According to one embodiment, a semiconductor light emitting device includes a plurality of chips, a first insulating layer provided between the chips, one p-side external terminal, and one n-side external terminal. Each of the chips includes a semiconductor layer, a p-side electrode, and an n-side electrode. Each of the chips is separated from each other. The one p-side external terminal is provided corresponding to one chip on the second face side. The p-side external terminal is electrically connected to the p-side electrode. The one n-side external terminal is provided corresponding to one chip on the second face side. The n-side external terminal is electrically connected to the n-side electrode.