Multi-Chip Package Structure for Low-Warpage Interposer Bonding
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in achieving efficient and reliable bonding between chip packages and interposer substrates, leading to issues with warpage and thermal expansion mismatch, which affect the bonding yield and mechanical strength of the chip package.
Innovation Solution
The process involves forming an interposer substrate with conductive pads and wiring layers, bonding it to a redistribution structure, and partially embedding a chip within the interposer substrate, which reduces warpage and enhances stiffness, thereby improving bonding yield and mechanical strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional bonding technologies are used to bond chip packages to interposer substrates, then the bonding process can be completed, but warpage and thermal expansion mismatch occur, leading to reduced bonding yield and mechanical strength
Solution Approach 1:
The chip package is divided into multiple chips arranged in an array, with each chip bonded to a corresponding interposer substrate. This segmentation allows for better stress distribution and reduced warpage compared to bonding a single large chip, while maintaining high bonding yield through the array configuration
Solution Approach 2:
Different regions of the chip package are designed with varying properties - the chips themselves have specific thermal expansion characteristics, while the interposer substrate provides mechanical support with different expansion properties. This local differentiation allows each component to optimize its function while managing thermal expansion mismatch at the bonding interfaces
2Reliability
If chip packages are bonded to interposer substrates, then electrical connections can be established, but thermal expansion mismatch reduces the mechanical strength of the bonding
Solution Approach 1:
The interposer substrate acts as an intermediary between the chips and the final package structure. It provides a transition layer that accommodates thermal expansion differences, absorbing stress during thermal cycling and protecting the bonding interfaces from damage, thereby maintaining mechanical strength
Solution Approach 2:
The chip package structure combines multiple materials with different thermal expansion properties - semiconductor chips, organic interposer substrates, and molding compounds. This composite construction allows each material to contribute its favorable properties while the overall structure manages thermal expansion mismatch through the combination
3Adaptability or versatility
If multiple chips are arranged in an array on interposer substrates, then the functionality and performance of the chip package can be enhanced, but the total thickness of the chip package increases
Solution Approach 1:
Multiple chips are arranged in a two-dimensional array on the interposer substrate rather than stacking them vertically. This lateral arrangement in the x-y plane allows for increased functionality and chip count without proportionally increasing the thickness in the z-direction, effectively using another dimension to solve the space constraint
Data Source
AI summary
A chip package is provided. The chip package includes a substrate structure including: a redistribution structure having a conductive pad; and an insulating layer under the redistribution structure. The chip package includes a first chip over the redistribution structure. The chip package includes a second chip under the substrate structure. A top portion of the second chip extends into the insulating layer from a bottom surface of the insulating layer, the bottom surface faces away from the first chip, and a portion of the insulating layer is between the second chip and the redistribution structure. The chip package includes a first molding layer over the redistribution structure and the first chip. A first sidewall of the first molding layer and a second sidewall of the redistribution structure are substantially level with each other.