Multi-chip Memory Package Small Substrate Design
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Solution Overview
Problem
Conventional multi-chip memory packages face issues with poor moisture resistivity and reliability due to exposed cut sides of substrates, which lead to peeling and Electrostatic Discharge (ESD) problems, and high fabrication costs due to limited circuitry layout and complex wire bonding with leadframes.
Innovation Solution
A multi-chip memory package design featuring a small substrate with a die pad, a substrate attached to the die pad, and an encapsulant, where the substrate's dimension is smaller than the encapsulant, and tie bars connect to the die pad and encapsulant, forming insulated cut ends to prevent ESD and reduce substrate exposure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a substrate with the same dimension as the memory card is used as a chip carrier, then the substrate can support multiple chips and provide circuit connectivity, but the exposed cut sides of the substrate cause poor moisture resistivity and poor reliability
Solution Approach 1:
The substrate is divided into two functional parts: a small substrate for mounting chips and providing circuit connectivity, and a separate leadframe structure for mechanical support and electrical connection. This segmentation allows the small substrate to be fully encapsulated while the leadframe extends to provide external connections.
Solution Approach 2:
The small substrate is mounted on the die pad of the leadframe structure, creating a nested configuration where the substrate is fully enclosed by the encapsulant along with the leadframe components. This nesting ensures complete coverage and protection of the substrate edges.
2Strength
If a substrate with the same dimension as the memory card is used, then circuit connectivity is provided, but the substrate is vulnerable to peeling due to stresses on the peripheries
Solution Approach 1:
The structural support function is separated from the circuit carrier function. The leadframe provides mechanical strength and stress distribution, while the small substrate focuses on electrical connectivity and chip mounting. This division allows the substrate to be smaller and more robust.
Solution Approach 2:
The package uses a composite structure combining the substrate material (for electrical properties) with the leadframe material (for mechanical strength). This composite approach provides both electrical connectivity and resistance to peeling stresses.
3Ease of manufacture
If a leadframe is used to replace the substrate, then packaging cost is reduced, but circuitry layout is limited and wire bonding becomes complicated
Solution Approach 1:
The leadframe provides the basic mechanical support and external connections, while the separate substrate handles the complex circuitry layout and wire bonding. This segmentation allows each component to be optimized for its specific function.
Solution Approach 2:
The small substrate acts as an intermediary between the leadframe and the chips, providing a suitable platform for complex circuit layouts and wire bonding operations, while the leadframe provides cost-effective mechanical support and external connections.
4Reliability
If the cut ends of tie bars or cut sides of substrate are exposed after singulation, then electrical connectivity is maintained, but ESD issues occur during packaging processes
Solution Approach 1:
The small substrate and leadframe components are nested together and fully encapsulated by the molding compound. This nesting ensures that all cut surfaces, including those of the tie bars and substrate, are covered and protected from atmospheric exposure.
Solution Approach 2:
The encapsulant acts as an intermediary protective layer between the exposed cut surfaces and the external environment, preventing ESD issues while maintaining electrical connectivity through the leadframe's external terminals.
Data Source
AI summary
Disclosed is a multi-chip memory package with a small substrate by using a die pad having an opening to substitute the chip-carrying function of a conventional substrate so that substrate dimension can be reduced. A substrate is attached under the die pad. A first chip is disposed on the substrate located inside the opening. A second chip is disposed on the die pad. An encapsulant encapsulates the top surface of the die pad, the top surface of the substrate, the first chip, and the second chip. The dimension of the substrate is smaller than the dimension of the encapsulant. In a preferred embodiment, a plurality of tie bars physically connect to the peripheries of the die pad and extend to the sidewalls of the encapsulant to have a plurality of insulated cut ends exposed from the encapsulant.