Multi-Chip Antenna Array Layout for Large Virtual MIMO Apertures
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Solution Overview
Problem
The integration of virtual MIMO antenna arrays in radar and telecommunication systems is economically unfeasible due to size differences between antennas and transceivers, requiring advanced substrates and complex packaging, especially with the shift to mmWave frequencies.
Innovation Solution
A multi-chip system where up-conversion and down-conversion circuits are integrated separately on distinct chips, allowing for optimized spacing and miniaturization of antennas, enabling the creation of large virtual arrays without advanced substrates or complex interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If virtual MIMO antenna arrays are integrated on a single chip, then spatial resolution and interference immunity are improved, but device complexity and manufacturing cost increase due to size differences between antennas and transceivers
Solution Approach 1:
The patent divides the MIMO antenna array into multiple separate chips, each containing a subset of antenna elements. This segmentation allows each chip to be manufactured independently with standardized transceiver-integrated antenna designs, avoiding the complexity of integrating all antenna elements on a single large substrate while maintaining the virtual array's spatial resolution capabilities through distributed antenna placement.
2Measurement precision
If antenna array size is increased to achieve larger virtual aperture, then measurement precision improves, but area and manufacturing cost increase
Solution Approach 1:
The patent transitions from a two-dimensional planar integration approach to a three-dimensional distributed architecture where multiple chips are stacked or arranged in space. This allows the virtual antenna array to achieve a large effective aperture by utilizing the third dimension (vertical stacking or spatial distribution) rather than expanding the substrate area horizontally, thereby maintaining high spatial resolution while minimizing the footprint of individual chips.
3Manufacturing precision
If advanced substrates and complex packaging are used to integrate antennas and transceivers, then integration precision improves, but manufacturing cost and device complexity increase
Solution Approach 1:
The patent segments the system into multiple standardized chips that can be manufactured using conventional fabrication processes. Each chip integrates a manageable number of antenna elements with their corresponding transceivers, allowing for standardized manufacturing without requiring advanced substrates or complex packaging techniques. This segmentation enables mass production of individual chips that can then be assembled into larger MIMO arrays using simpler interconnection methods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the efficient creation of large virtual MIMO antenna arrays with reduced costs and complexity, achieving finer spatial resolution and improved immunity to interference without the need for special packaging or substrates.
Implementation Method 1
Each transmitting chip comprises an integrated transmitting antenna and an integrated up-conversion circuit
Implementation Method 2
Each receiving chip comprises an integrated receiving antenna and an integrated down-conversion circuit
Implementation Method 3
mmWave sensors transmit signals with a wavelength which is in the millimeter range
Data Source
Figure 1
Figure 2A~2C
Figure 2D~2E
AI summary
A multi-chip system (1) configured as an antenna array (2), wherein said multi-chip system comprises: - at least two transmitting sets (130) distributed over one or more transmitting chips (100), wherein a transmitting set (130) comprises an integrated transmitting antenna (110) and an integrated up-conversion circuit (120); and/or - at least two receiving chips (200), wherein a receiving chip (200) comprises at least one integrated receiving antenna (210) and at least one integrated downconversion circuit (220).