Multi-chip Package with Horizontal Conduction Layer
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Solution Overview
Problem
Existing power semiconductor device packages face challenges in minimizing on-state resistance and static losses, particularly when multiple chips are used in parallel, as the complexity and size of the heat dissipation systems increase with higher power losses.
Innovation Solution
A package design featuring multiple power semiconductor chips connected in parallel, with a lead frame structure and a horizontally extending conduction layer at the top side or footprint side, allowing for efficient heat dissipation and reduced on-state resistance through optimized terminal connections and heat management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If multiple power semiconductor chips are connected in parallel to reduce on-state resistance and static losses, then the total on-state resistance and static losses are reduced, but the complexity and size of the heat dissipation system increase
Solution Approach 1:
The patent combines multiple power semiconductor chips (first power semiconductor chip and second power semiconductor chip) into a single integrated package with shared heat dissipation structures. The first heat dissipation structure and second heat dissipation structure are integrated within the same package body, allowing heat from multiple chips to be managed through coordinated thermal pathways rather than separate independent systems. This merging approach reduces overall system complexity while maintaining the low on-state resistance benefits of parallel chip connections.
Solution Approach 2:
The package structure serves multiple functions simultaneously: it provides electrical connections for parallel chip operation, mechanical support for multiple chips, and integrated heat dissipation for all chips. The lead frame structure and heat dissipation structures are designed to handle both electrical current paths and thermal paths in a unified manner, reducing the need for separate specialized components and thereby reducing system complexity.
2Loss of energy
If multiple power semiconductor chips are connected in parallel to reduce on-state resistance, then the total on-state resistance is reduced, but the package size increases
Solution Approach 1:
The patent utilizes three-dimensional vertical stacking and layered arrangements within the package. Multiple power semiconductor chips are arranged in a compact configuration where heat dissipation structures extend in vertical and lateral dimensions. The first and second heat dissipation structures are positioned at different levels and orientations, allowing efficient heat extraction from multiple chips without requiring a proportionally larger footprint area. This dimensional optimization enables reduced on-state resistance through parallel chips while controlling package area growth.
3Loss of energy
If multiple power semiconductor chips are connected in parallel to reduce on-state resistance, then the total on-state resistance is reduced, but the package volume increases
Solution Approach 1:
The patent employs a nested arrangement where power semiconductor chips are integrated within the package body in a space-efficient manner. The first power semiconductor chip and second power semiconductor chip are positioned to utilize internal package space effectively, with heat dissipation structures nested around and between the chips. The lead frame structure and electrical connections are routed through available spaces within the package volume, allowing multiple chips to be accommodated without a linear increase in overall package volume.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves a significantly reduced total on-state resistance and static losses, enabling smaller, more efficient power semiconductor packages with improved heat dissipation capabilities.
Implementation Method 1
a horizontally extending conduction layer at the package top side or at the package footprint side, wherein the conduction layer is electrically connected with each of the second load terminals of the plurality of power semiconductor chips
Data Source
AI summary
A package includes a package body with a package top side, package footprint side and package sidewalls extending from the package footprint side to the package top side; power semiconductor chips electrically connected in parallel and each having first and second load terminals and being configured to block a blocking voltage and conduct a chip load current between the load terminals; a lead frame structure configured to electrically and mechanically couple the package to a carrier with the package footprint side facing the carrier, the lead frame structure including first outside terminals extending out of the package body for interfacing with the carrier. Each first load terminal is electrically connected, at least by one package body internal connection member, to at least two of the first outside terminals. A horizontally extending conduction layer at the package top side or footprint side is electrically connected with each second load terminal.