Multi-Chip Package Structure With 3D RDL Stacking
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Solution Overview
Problem
Existing package structures integrating multiple chips face challenges in achieving a smaller size while maintaining better quality or performance.
Innovation Solution
A package structure comprising at least one first chip, a second chip, a plurality of fourth chips, redistribution layers, and dielectric bodies, with conductive members connecting the chips and redistribution layers, allowing for a compact design and improved electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple chips are integrated into a single package structure, then functionality and performance are improved, but package size increases
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement of chips to a three-dimensional stacked configuration. Multiple chips (first chip, second chip, third chip) are arranged vertically along the thickness direction, with redistribution layers and dielectric bodies interleaved between them. This vertical stacking enables multiple chips to be integrated within a compact footprint, improving functionality while controlling package size.
Solution Approach 2:
The patent implements a nested structure where redistribution layers and dielectric bodies are embedded within and between chip layers. The first redistribution layer is disposed on the first chip, the second redistribution layer is embedded in the second dielectric body, and these intermediate structures are nested within the overall package volume. This nesting approach maximizes space utilization, allowing multiple functional layers to coexist in a compact three-dimensional arrangement.
2Volume of moving object
If chips are arranged in a compact configuration, then package size is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent divides the package structure into distinct modular segments: first chip, first dielectric body, first redistribution layer, second chip, second dielectric body, second redistribution layer, and third chip. Each segment can be independently prepared and then assembled through stacking. This segmentation simplifies manufacturing by allowing parallel processing of individual components before final integration, reducing the overall manufacturing complexity despite the compact three-dimensional configuration.
3Reliability
If multiple redistribution layers are added to connect chips, then electrical connectivity is improved, but structural complexity increases
Solution Approach 1:
The patent combines multiple functions into the dielectric bodies and redistribution layers. The dielectric bodies serve both as insulating layers and as structural support elements that hold the redistribution layers. The redistribution layers are integrated within the dielectric structures rather than being separate components, reducing the total number of discrete elements. This merging approach improves electrical connectivity between chips while minimizing the increase in structural complexity.
Data Source
AI summary
A package structure including a first chip, a second chip, a plurality of fourth chips, a first redistribution layer, a second redistribution layer, a third redistribution layer, a first dielectric body, a second dielectric body, and a conductive member is provided. The first chip is disposed between the first redistribution layer and the third redistribution layer. The conductive member is disposed between the first redistribution layer and the second redistribution layer. The second redistribution layer is electrically connected to the first chip through the conductive member and the first redistribution layer. The second redistribution layer is disposed between the second chip and the fourth chip. Two of the fourth chips are electrically connected to each other through the second redistribution layer and the second chip. The first dielectric body covers the first chip, the second chip, the first redistribution layer, the second redistribution layer, the third redistribution layer, and the conductive member. The second dielectric body covers the second redistribution layer.