Multi-chip Package Stacking Different Sized Chips
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Solution Overview
Problem
The challenge lies in manufacturing a multi-chip package with stacked semiconductor chips of different sizes without using multiple-layered wires, which is necessary to prevent insulation problems and crosstalk, while maintaining a compact size and weight, as existing technologies require wire bonding that increases package size due to the need for minimum interval spaces and areas.
Innovation Solution
The solution involves stacking semiconductor chips with pad groups having pads at the same coordinates, allowing for vertical alignment and connection without multilayered wires, using through-hole via pads and bumps for electrical connection, and arranging pad groups at central or edge regions for efficient packaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding is used to connect stacked semiconductor chips, then electrical connections can be established, but the package size increases due to minimum interval spaces and area requirements for insulation and crosstalk prevention
Solution Approach 1:
The patent transitions from planar wire bonding to three-dimensional vertical stacking with through-hole via pads. Multiple chips are stacked in the vertical dimension with pads extending through holes, allowing electrical connections without requiring lateral interval spaces, thus reducing package area while maintaining connection reliability
Solution Approach 2:
The patent implements nested stacking where smaller chips are positioned on top of larger chips, and through-hole via pads extend through multiple chip layers. This nesting approach allows efficient space utilization and reduces the overall package footprint compared to wire bonding methods
2Reliability
If multiple-layered wires are used for stacking different sized chips, then electrical connections can be achieved, but insulation problems and crosstalk occur
Solution Approach 1:
The patent extracts the wire bonding element entirely and replaces it with through-hole via pads that extend vertically through chip layers. This elimination of lateral wires removes the source of crosstalk and insulation problems while maintaining electrical connection functionality through vertical pad structures
Solution Approach 2:
The through-hole via pads serve as intermediary structures that provide electrical connections between stacked chips without requiring lateral wire paths. These vertical pad intermediaries eliminate crosstalk by providing direct, isolated connection paths through each chip layer
3Adaptability or versatility
If semiconductor chips of different sizes are stacked, then system-in-package functionality is achieved, but manufacturing complexity increases compared to wafer level packaging
Solution Approach 1:
The patent creates a universal stacking methodology using through-hole via pads that can accommodate chips of different sizes and types. The same basic stacking approach works for various chip configurations, simplifying manufacturing compared to custom wire bonding solutions for each chip combination
Data Source
AI summary
Provided is a multi-chip package in which a plurality of semiconductor chips having different sizes are stacked. A multi-chip package may include a substrate, and a plurality of semiconductor chips stacked on the substrate, each of the plurality of semiconductor chips having a different size. Each of the plurality of semiconductor chips including a pad group and a reference region associated with the pad group, each pad group having a plurality of pads, and the plurality of pads in each pad group located at same coordinates with respect to the associated reference region, and each of the plurality of semiconductor chips having their reference regions vertically aligned.