Multi-Chip Package with Vertically Embedded Dies
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Solution Overview
Problem
The integration of multiple semiconductor dies within a single package is hindered by thermal expansion mismatches, leading to structural defects and warpage issues, which complicates the formation of compact, high-density circuitry necessary for advanced electronics.
Innovation Solution
A multi-chip package design featuring a coreless substrate with vertically arranged dies and a bumpless build-up layer (BBUL) process, which embeds dies within a substrate using insulating and routing layers to create electrical connections and minimize thermal expansion effects, eliminating the need for package-on-package technology and reducing warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiples of packaged die are coupled together for advanced functionality, then device complexity and functionality are improved, but structural defects and warpage occur due to thermal expansion mismatches
Solution Approach 1:
The patent introduces an intermediate substrate structure with routing layers and insulating layers that acts as a mediator between multiple dies. This substrate serves as a common platform that accommodates thermal expansion differences, preventing direct stress transmission between dies with different CTE values, thereby eliminating structural defects while maintaining multi-die functionality.
Solution Approach 2:
The patent changes the physical parameters of the package structure by using a substrate-based embedding approach rather than direct die stacking. The routing layers and insulating layers create a compliant structure that can absorb thermal expansion parameter variations, allowing multiple dies with different CTE values to coexist without warpage or structural failure.
2Area of moving object
If semiconductor packages are designed to be more compact with larger circuit density, then device size is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar circuit layout to three-dimensional vertical stacking of multiple dies within a compact footprint. By utilizing the vertical dimension and embedding dies within a substrate, the design achieves higher circuit density without proportionally increasing manufacturing complexity, as the substrate provides a standardized platform for integration.
3Quantity of substance
If package-on-package technology is used to achieve compact design, then device density is improved, but warpage and thermal expansion issues worsen
Solution Approach 1:
The patent replaces the package-on-package direct coupling approach with an intermediate substrate structure. This substrate with its routing layers and insulating layers acts as a stress-absorbing intermediary that decouples the thermal expansion behaviors of stacked dies, maintaining high device density while eliminating warpage through compliant structural design.
Data Source
AI summary
An apparatus includes a substrate having a land side having a plurality of contact pads and a die side opposite the land side. The apparatus includes a first die and a second die wherein the first die and second die are embedded within the substrate such that the second die is located between the first die and the land side of the substrate.