Multi-Chip Semiconductor Interconnections Using Passive Bridge
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Solution Overview
Problem
In silicon photonics devices, traditional wire bonding methods result in longer interconnect paths with higher parasitic inductance, leading to poorer electrical performance and challenges in accessing V-grooves for optical fiber connections, especially in flip-chip integration.
Innovation Solution
A multi-chip semiconductor device with a connecting passive chip using solder bumps for flip-chip bonding between chips and the substrate, allowing for shorter interconnect paths and accommodating manufacturing variations, while enabling levelled surfaces for reliable connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If wire bonding is used for chip-to-chip and chip-to-substrate interconnections, then the manufacturing process is flexible and low cost, but the interconnect paths are long resulting in higher parasitic inductance and poorer electrical performance
Solution Approach 1:
The patent transitions from planar wire bonding to three-dimensional flip-chip stacking, where chips are vertically arranged and connected through the substrate. This dimensional change shortens interconnect paths significantly, reducing parasitic inductance while maintaining manufacturing feasibility through established flip-chip processes
Solution Approach 2:
The substrate is used as an intermediary carrier that hosts both the chips and the interconnection structures. By placing chips on opposite sides of the substrate and using through-substrate vias as intermediaries, the patent achieves short interconnect paths while maintaining flexibility in chip placement and manufacturing
2Reliability
If flip-chip integration is used to provide shorter interconnect paths, then electrical performance improves, but the V-grooves for optical fiber connections are not easily accessible after assembly
Solution Approach 1:
The patent segments the device into multiple functional layers: optical interface layer (with V-grooves), photonic chip layer, electronic chip layer, and substrate layer. This segmentation allows the V-grooves to be positioned on the top surface for easy optical fiber access while the active surfaces of chips face each other internally for flip-chip bonding, resolving the conflict between accessibility and electrical performance
3Adaptability or versatility
If multiple chips are integrated in a multi-chip module, then functionality is enhanced, but the packaging footprint increases
Solution Approach 1:
The patent employs vertical stacking of multiple chips (photonic chip, electronic chip, substrate) to achieve three-dimensional integration. This transforms the packaging from a two-dimensional spread-out layout to a compact three-dimensional structure, significantly reducing the packaging footprint while maintaining enhanced functionality through multi-chip integration
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces parasitic inductance, improves electrical performance, and allows for closer chip placement, enhancing package efficiency and reliability with reduced assembly steps and radiation issues.
Implementation Method 1
a connecting passive chip bridging the first chip, the added second chip and the substrate by solder bumps
Data Source
AI summary
A multi-chip semiconductor device with multi-level structure including a substrate with a top substrate surface, a cavity with a depth in the substrate, a first chip having a top first chip surface with a first chip height, optionally including a second chip having a top second chip surface with a second chip height, and a connecting passive chip bridging the first chip, the second chip and the substrate by solder bumps wherein the solder bumps enable the connecting passive chip to be level.