Multi-Chip Photonic Memory Fabrics for High-Bandwidth, Low-Energy Links
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Solution Overview
Problem
Current computing systems face challenges with high power consumption and inefficient data movement due to limitations in memory latency, bandwidth, and signal integrity, particularly in artificial intelligence computing, where existing SerDes blocks and high bandwidth memory systems impose constraints on data transmission and processing efficiency.
Innovation Solution
Implementing a hybrid electronic-photonic network-on-chip (NoC) within circuit packages, utilizing bidirectional photonic channels for intra- and inter-chip communications, which reduces power consumption by minimizing data movement and optimizing data locality, and incorporating a novel clocking scheme and dot product engine for efficient MAC operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If SerDes blocks are used to convert parallel messages into serial bit streams for chip-level interconnects, then data transmission between chips is enabled, but significant energy is expended in moving data within the chip to the SerDes and then from the SerDes into other chips
Solution Approach 1:
The patent replaces electrical signal transmission through SerDes blocks with optical signal transmission through photonic channels. Light-based communication substitutes for electrical conversion and transmission, eliminating the need for serializer/deserializer blocks and reducing energy consumption associated with electrical signal processing and conversion.
Solution Approach 2:
The patent introduces photonic channels as an intermediary medium for data transmission between processing elements. These optical channels serve as a mediator that directly connects processing elements without requiring conversion through electrical SerDes blocks, thereby reducing energy expenditure in data movement.
2Productivity
If HBM memory is mounted on a silicon interposer with pins running over electrical wires at over 3 GHz, then memory bandwidth is increased, but signal integrity constraints and packaging complexity increase significantly
Solution Approach 1:
The patent replaces electrical wire connections with optical fiber connections for memory interconnects. This substitution eliminates the need for high-frequency electrical signaling constraints and complex packaging requirements, while maintaining high bandwidth through photonic transmission channels.
Solution Approach 2:
The patent transitions from two-dimensional electrical interconnects on a silicon interposer to three-dimensional optical pathways using optical fibers. This dimensional change allows for more flexible routing and reduces the constraints imposed by planar packaging limitations.
3Loss of time
If memory elements are placed close to client devices to reduce latency, then memory access speed is improved, but the number and arrangement of HBM stacks are highly constrained
Solution Approach 1:
The patent introduces optical fibers as intermediary transmission media that can span longer distances with low loss. This allows memory elements to be positioned farther from client devices without significantly increasing latency, thereby providing greater flexibility in memory stack arrangement and system packaging.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves reduced power consumption and increased processing speed by minimizing data movement and energy losses, while providing efficient data transfer and computation through photonic channels, particularly suitable for artificial neural networks.
Implementation Method 1
bidirectional photonic channels (e.g., implemented in a photonic integrated circuit in a separate layer or chip of the package)
Data Source
AI summary
Multi-chip electro-photonic networks for interconnecting multiple circuit packages via photonic channels. Examples of a computing system include a first circuit package, a second circuit package, and one or more inter-chip bidirectional photonic channels interconnecting the first and second circuit packages. The first circuit package can include one or more memory nodes. The second circuit package can include multiple compute nodes and intra-chip bidirectional photonic channels interconnecting the compute nodes.