Multi-Chip PHY Deskewing with Clock Phase Alignment
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Solution Overview
Problem
The misalignment of data and clock signals between functional blocks in semiconductor chips leads to significant latency during information transfer, which existing methods fail to address efficiently.
Innovation Solution
A circuit is employed to synchronize a local clock with a global clock using a barrel shifter and control logic, adjusting the phase of the local clock to align with the global clock, and implementing a FIFO mode to increase timing margin, thereby achieving a synchronous clock-domain crossing with reduced latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data signals and clock signals are sent between functional blocks on separate dies, then information transfer capability is improved, but signal misalignment occurs leading to increased latency
Solution Approach 1:
The patent applies preliminary action by performing symbol locking and phase alignment before data transfer operations. The circuit sweeps the local clock across phases and detects edge transitions to pre-establish proper synchronization, ensuring that when data transfer occurs, the signals are already aligned and no additional latency is introduced during actual data operations
Solution Approach 2:
The patent implements feedback mechanisms where the circuit continuously monitors the alignment between data and clock signals. Control logic detects edge transitions and adjusts the local clock phase accordingly, creating a closed-loop system that maintains synchronization and prevents latency accumulation during data transfer between functional blocks
2Reliability
If clock phase adjustment is performed to align data and clock signals, then signal synchronization is improved, but circuit complexity increases
Solution Approach 1:
The patent introduces an intermediary barrel shifter circuit that mediates between the incoming clock signal and the local clock. This barrel shifter provides a structured way to adjust clock phases by shifting bits in a register, creating an intermediate representation that can be easily controlled and adjusted without requiring complex phase-locked loop circuits or multiple clock sources
Solution Approach 2:
The patent changes the parameter of clock phase by sweeping the local clock across different phases and detecting edge transitions. By systematically varying the phase parameter and identifying the optimal alignment point through detection logic, the circuit achieves reliable synchronization through controlled parameter adjustment rather than complex hardware modifications
3Reliability
If FIFO mode is implemented to increase timing margin, then timing reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-synchronizing the local clock with the incoming clock before data is loaded into the FIFO buffer. By establishing proper phase alignment and timing relationships in advance, the FIFO operates within well-defined timing margins, eliminating the need for complex timing recovery circuits or additional synchronization stages that would increase device complexity
Data Source
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AI summary
Systems, apparatuses, and methods for implementing a deskewing method for a physical layer interface on a multi-chip module are disclosed. A circuit connected to a plurality of communication lanes trains each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window. Next, the circuit symbol rotates each lane by a single step responsive to determining that all of the plurality of lanes have an incorrect symbol alignment. Responsive to determining that some but not all of the plurality of lanes have a correct symbol alignment, the circuit symbol rotates lanes which have an incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates lanes which have a correct symbol alignment and adjusts a phase of a corresponding global clock to compensate for missed symbol rotations.