Multi-Chip PoE Power Allocation for Fast Port Expansion
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Solution Overview
Problem
Existing PoE systems with multiple communication ports face inefficiencies due to long control cycles and limited port expansion capabilities, especially when using an MCU, and systems with a single PSE chip are limited by the number of ports they can support.
Innovation Solution
A multi-chip system with prioritized chips that execute power management methods, including initialization and power supply procedures, allowing dynamic or static power calculations, and real-time power adjustments to balance power distribution among communication ports without an MCU, enabling flexible port expansion and reduced control cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If an MCU is used to manage multiple PSE chips, then power management control is achieved, but the control cycle becomes long (tens or hundreds of milliseconds) and the system cost increases
Solution Approach 1:
The patent segments the power management function from the central MCU and distributes it to individual PSE chips. Each PSE chip independently manages its own power allocation and communicates with the MCU only for status reporting, eliminating the need for the MCU to periodically poll all PSE chips and reducing the control cycle significantly.
Solution Approach 2:
The PSE chips are equipped with embedded controllers that enable them to autonomously perform power management tasks including power allocation, status monitoring, and communication with other PSE chips. This self-service capability removes the burden from the MCU, reducing control cycle time while maintaining comprehensive power management.
2Ease of operation
If an MCU is used to manage multiple PSE chips, then power management is achieved, but the number of supported ports is limited by MCU software
Solution Approach 1:
The system is segmented into multiple independent PSE chips, each capable of managing its own set of communication ports. This modular architecture allows the system to support any number of ports by simply adding more PSE chips, without being constrained by the MCU's software limitations.
Solution Approach 2:
Each PSE chip is designed as a universal module that can independently manage power for multiple communication ports. The chips communicate with each other through a standardized bus interface, allowing flexible configuration and expansion of the system to accommodate varying numbers of ports without requiring changes to the MCU software.
3Ease of manufacture
If only a single PSE chip is used, then system cost is reduced, but the number of supported ports is limited to the single chip's ports
Solution Approach 1:
The system uses multiple independent PSE chips instead of a single chip, with each chip managing a subset of communication ports. This segmentation allows the system to scale from a cost-effective single-chip configuration to multi-chip configurations as port requirements increase, maintaining cost efficiency while enabling port expansion.
Solution Approach 2:
Multiple PSE chips are merged into a unified power management system through a standardized communication bus. The chips work together as a coordinated team, with each chip independently managing its assigned ports while sharing system-wide power allocation information, thereby achieving port expansion without proportionally increasing system cost.
4Adaptability or versatility
If multiple PSE chips are used with an MCU, then port expansion is possible, but the system becomes costly
Solution Approach 1:
The patent extracts the power management control logic from the expensive MCU and places it directly into the PSE chips. This extraction eliminates the need for the MCU to perform complex power management calculations and communication with each PSE chip, reducing the MCU's processing burden and allowing the use of lower-cost MCU configurations while supporting multiple PSE chips and expanded ports.
Solution Approach 2:
Each PSE chip is equipped with an embedded controller that enables it to autonomously perform power management functions including power allocation, status monitoring, and inter-chip communication. This self-service capability eliminates the need for expensive high-performance MCUs, as the power management intelligence is distributed to the PSE chips themselves, reducing overall system cost while enabling port expansion.
Data Source
AI summary
A power management method includes: executing an initialization procedure to obtain a remaining available power value; sequentially executing a power supply procedure for each of the communication ports; calculating the power consumed by each of the communication ports that are powered on; summing the power consumed by all the communication ports that are powered on to obtain a local used power value; subtracting the used power value of the storage unit of the chip having the previous priority and the local used power value from the total power value to obtain a second remaining available power value; and in response to that the second remaining available power value is greater than or equal to 0, adding the local used power value to the used power value of the storage unit of the chip having the previous priority to obtain the used power value.