Multi-chip Semiconductor Power Device Thermal Management
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Solution Overview
Problem
Current semiconductor packaging methods are costly and inefficient, particularly for power applications, as they do not effectively manage thermal dissipation and component separation, leading to reduced performance and lifetime of semiconductor devices.
Innovation Solution
A semiconductor device configuration featuring a 'power plane' with vertically structured power semiconductor chips and a 'logic plane' separated by a contact clip, where the power chips are mounted on carriers and encapsulated in an insulating material, allowing for efficient thermal management and compact packaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If multiple semiconductor chips are packaged in a stacked configuration, then the component size is reduced and manufacturing cost is decreased, but thermal dissipation management becomes more difficult
Solution Approach 1:
The patent divides the semiconductor device into distinct functional segments: a power plane containing power semiconductor chips and a logic plane containing logic chips, separated by an intermediate carrier. This segmentation allows independent thermal management for each functional block, addressing the thermal dissipation challenge while maintaining the compact stacked configuration.
Solution Approach 2:
The patent introduces an intermediate carrier with a mounting surface that acts as a mediator between the power semiconductor chips and logic chips. This intermediate structure provides thermal management capabilities and electrical isolation, enabling effective heat dissipation from power chips while supporting the logic chips above, thus resolving the thermal management issue in stacked packaging.
2Adaptability or versatility
If power semiconductor chips and logic chips are integrated in the same package, then device functionality is enhanced, but thermal robustness and performance are reduced
Solution Approach 1:
The patent segments the device into a power plane and a logic plane, with power semiconductor chips mounted on a first carrier and logic chips mounted on a second carrier separated by an intermediate carrier. This spatial segmentation isolates the thermally sensitive logic chips from the heat-generating power chips, enhancing thermal robustness while maintaining integrated functionality.
Solution Approach 2:
The patent applies local quality by providing different structural characteristics to different regions: the power plane area has structures optimized for heat dissipation and electrical connection, while the logic plane area has structures optimized for thermal isolation and signal integrity. This localized optimization allows both power and logic functions to operate reliably in the same package.
3Reliability
If semiconductor chips are mounted on electrically conductive carriers, then electrical connectivity is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The intermediate carrier is designed with multi-functionality: it serves as an electrical connection element between power and logic chips, provides thermal management, offers mechanical support, and enables precise alignment. This universal structure simplifies manufacturing by consolidating multiple functions into a single component rather than requiring separate elements for each function.
Data Source
AI summary
A semiconductor device includes a first semiconductor power chip mounted over a first carrier and a second semiconductor power chip mounted over a second carrier. The semiconductor device further includes a contact clip mounted over the first semiconductor power chip and on the second semiconductor power chip. A semiconductor logic chip is mounted over the contact clip.