Multi-chip Power Semiconductor Package with Integrated Lead Frame
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Solution Overview
Problem
Conventional multi-chip power semiconductor packages face reliability issues due to stray inductance and electromagnetic interference (EMI) caused by wire bonding and clip bonding methods, which increase resistance and lead to defects and performance problems in high-power density applications.
Innovation Solution
A multi-chip package design that eliminates wire bonding and clip bonding by physically connecting source and drain segments via a lead frame, using a flip-chip configuration with gate, source, and drain electrodes on the same side of the semiconductor chips, reducing stray inductance and improving connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding or clip bonding is used to connect drain electrode to neighboring chip's source electrode, then electrical connectivity between chips is achieved, but stray inductance increases and reliability decreases
Solution Approach 1:
The patent merges the drain electrode of one chip with the source electrode of another chip by forming them as a single integrated electrode structure on the same substrate. This eliminates the need for separate wire bonding or clip bonding connections, thereby removing the stray inductance and EMI sources associated with those bonding methods while maintaining electrical connectivity.
Solution Approach 2:
The patent extracts and eliminates the wire bonding and clip bonding processes from the manufacturing sequence. By redesigning the electrode configuration to allow direct integration of drain and source electrodes, the harmful bonding materials and processes are completely removed from the system, resolving the inductance and reliability issues they cause.
2Reliability
If wire bonding is used to connect chips, then electrical connectivity is achieved, but bonding defects such as short or open wire occur
Solution Approach 1:
The patent replaces the mechanical wire bonding process with an integrated electrode structure where drain and source electrodes are formed as continuous conductive paths on the substrate. This substitution eliminates the mechanical bonding steps that are prone to defects like short circuits and open wires, achieving both connectivity and manufacturing precision.
3Reliability
If clip bonding is used to connect chips, then electrical connectivity is achieved, but fatal defects such as short-circuit fault and chip crack occur
Solution Approach 1:
The patent merges the clip bonding step with the electrode formation process by designing the drain and source electrodes as integrated structures. This eliminates the need for separate clip bonding that causes structural stress and potential cracks, maintaining both electrical connectivity and structural integrity of the chip assembly.
Data Source
AI summary
A multi-chip package of power semiconductor includes a lead frame, a first segment group, a second segment group, a first power semiconductor chip and a second power semiconductor chip. The lead frame includes a first segment group having a first gate segment, a first source segment, and a first drain segment that are separated from each other. The second segment group has a second gate segment, a second source segment, and a second drain segment that are separated from each other. The first power semiconductor chip is formed on the first segment group. The second power semiconductor chip is formed on the second segment group. The first source segment is physically connected to the second drain segment.