Multi-chip Structure Stacking Memory on Programmable IC
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing multi-chip structures require interposers and physical layer interfaces, which increase processing costs, power consumption, and die area usage, and limit flexibility and customization.
Innovation Solution
A multi-chip structure is formed by stacking memory dies directly on a die with a programmable integrated circuit (IC), eliminating the need for interposers and physical layer interfaces, and incorporating a memory controller for high bandwidth memory access, allowing for customizable logic and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If interposers and physical layer interfaces are used in multi-chip structures, then connection reliability is improved, but processing costs increase
Solution Approach 1:
The patent removes the interposer component from the multi-chip structure, eliminating it entirely. The memory dies are stacked directly on the programmable logic device die without an interposer layer, thereby reducing processing costs while maintaining connection reliability through direct die-to-die bonding interfaces.
Solution Approach 2:
The patent merges the functions of the interposer and physical layer interfaces directly into the programmable logic device die. The PLD die integrates both the programmable logic functionality and the physical layer interface circuits, eliminating the need for separate interposer structures and reducing overall manufacturing complexity.
2Reliability
If interposers and physical layer interfaces are used in multi-chip structures, then connection stability is improved, but power consumption increases
Solution Approach 1:
The patent extracts and removes the separate physical layer interface circuits from the interposer structure, integrating them directly into the PLD die. This eliminates redundant signal transmission paths and reduces overall power consumption while maintaining connection stability through direct integrated interfaces.
Solution Approach 2:
The patent combines the physical layer interface functionality with the programmable logic device, creating a unified integrated structure. This merging eliminates the need for separate interface circuits on the interposer, reducing power consumption by eliminating redundant signal conditioning and transmission through multiple interfaces.
3Area of stationary object
If interposers are used in multi-chip structures, then die area coverage is improved, but device complexity increases
Solution Approach 1:
The patent extracts the interposer component from the multi-chip structure entirely, eliminating the complex multi-layer interposer architecture. The memory dies are stacked directly on the PLD die, significantly reducing structural complexity while achieving efficient space utilization through vertical stacking.
Solution Approach 2:
The patent transitions from a planar two-dimensional layout with interposers to a three-dimensional vertical stacking architecture. By stacking memory dies vertically on the PLD die, the patent achieves high die area coverage and efficient space utilization without requiring complex interposer structures, thereby reducing overall device complexity.
4Ease of manufacture
If memory dies are stacked directly on programmable logic device die, then manufacturing simplicity is improved, but connection precision requirements increase
Solution Approach 1:
The patent introduces alignment marks and registration features as intermediary elements on the die surfaces. These markers serve as reference points that guide the precise alignment of memory dies during the stacking process, enabling direct die-to-die bonding with high precision while maintaining manufacturing simplicity through standardized alignment procedures.
Data Source
AI summary
Some examples described herein provide for a multi-chip structure including one or more memory dies stacked on a die having a programmable integrated circuit (IC). In an example, a multi-chip structure includes a package substrate, a first die, and a second die. The first die includes a programmable IC, and the programmable IC includes a memory controller. The first die is on and attached to the package substrate. The second die includes memory. The second die is stacked on the first die. The memory is communicatively coupled to the memory controller.