Multi-chip semiconductor package with tilt pads and TSVs
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Solution Overview
Problem
Conventional multi-chip packages are large, reducing mounting density and causing signal delays due to complex processes and the need for distinct substrate configurations for each chip selection terminal, leading to increased production costs and reduced productivity.
Innovation Solution
A semiconductor package design featuring through silicon vias, selection pads, tilt pads, and tilt conductive structures that allow for vertical stacking of chips with a chip-selection function, using a cost-effective method that eliminates the need for complex substrate configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional multi-chip packages are formed by stacking packages with substrates, then chip selection functionality is achieved, but package size becomes large and mounting density is reduced
Solution Approach 1:
The patent transitions from horizontal substrate-based chip selection to vertical stacking architecture. Multiple chips are stacked in the vertical dimension with selection pads positioned on the lower surface, allowing chip selection without requiring large horizontal substrate areas. This dimensional change enables compact package size while maintaining chip selection capability through vertical signal routing via TSVs.
Solution Approach 2:
The lower surface of each chip is designed with multiple selection pads that can selectively connect to different chips in the stack through TSVs. This universal selection mechanism allows any chip in the stack to be individually accessed through the same lower surface interface, eliminating the need for separate substrate configurations for each chip and reducing overall package size.
2Ease of operation
If conventional multi-chip packages use substrates with connection wirings for each chip selection terminal, then chip selection is enabled, but device complexity and production cost increase
Solution Approach 1:
The patent extracts the chip selection functionality from the substrate and integrates it directly into the chip structure. Selection pads are formed on the lower surface of each chip itself, and TSVs provide direct vertical connections to other chips. This eliminates the need for complex substrate-based connection wirings and different substrate configurations for each chip, thereby reducing device complexity and production cost.
Solution Approach 2:
The patent merges the chip selection terminal functionality with the chip structure itself. The selection pads and TSVs are integrated into each chip, combining the chip body and selection interface into a unified structure. This merging eliminates the separate substrate layer and its complex wiring, simplifying the overall device architecture while enabling chip selection.
3Ease of operation
If conventional multi-chip packages are manufactured by stacking completed packages, then chip selection functionality is achieved, but manufacturing complexity and time increase
Solution Approach 1:
The patent incorporates chip selection pads and TSV connections into each chip during the chip manufacturing process itself, before the stacking assembly. The selection pads are formed on the lower surface and TSVs are pre-configured with appropriate connection patterns. This preliminary preparation enables simplified stacking and assembly, improving manufacturing efficiency while maintaining chip selection functionality.
Solution Approach 2:
The patent segments the chip selection functionality into individual chip components (selection pads and TSVs) that can be independently manufactured and then assembled. Each chip is prepared as a self-contained unit with its own selection interface, allowing parallel manufacturing and simplifying the stacking process. This segmentation improves productivity by enabling independent chip fabrication and assembly.
4Ease of operation
If conventional multi-chip packages use standard chip sizes with stacking, then chip selection is enabled, but signal transmission route length increases causing signal delay
Solution Approach 1:
The patent uses vertical stacking with TSVs to create direct vertical signal pathways between chips. The selection pads on the lower surface connect directly to corresponding pads on adjacent chips through vertical TSV connections, eliminating long horizontal signal routes through substrates. This vertical dimensionality change significantly reduces signal transmission distance and delay while maintaining chip selection terminal isolation.
Data Source
AI summary
A semiconductor chip includes a semiconductor device with an upper surface and a lower surface opposite to the upper surface. The semiconductor device includes an input terminal, a plurality of through silicon vias, a plurality of selection pads, a plurality of tilt pads and a plurality of tilt conductive structures. The through silicon vias are extended through the semiconductor device. The selection pads are located on the lower surface The tilt pads are located on the upper surface and connected to the selection pads through the through silicon vias respectively. Each tilt pad includes a pad surface that is non-parallel to the upper surface. A lower end of each tilt conductive structure is in contact with the pad surface of each tilt pad, and an upper end of each tilt conductive structure is vertically overlapped with an immediately-adjacent one of the tilt pads.