Multi-chip Semiconductor Apparatus With Exposed Probe Pads

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Solution Overview

Problem

Current semiconductor packaging technologies face challenges in performing probing tests on multi-chip semiconductor apparatuses after they are completely packaged, as the probe pads are not accessible from the outside due to being connected through through-silicon vias (TSVs).

Innovation Solution

The solution involves stacking semiconductor chips with through-silicon vias (TSVs), where each chip has exposed bump pads and probe pads connected by conductive layers, allowing for electrical connections within the chip and enabling probing tests even after packaging by connecting specific conductive layers between the probe and bump pads.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If through-silicon vias (TSVs) are used to connect semiconductor chips in a stacked configuration, then integration density and miniaturization are improved, but probe pads become inaccessible for probing tests after packaging

Engineering Contradiction:
Improveintegration densityVSAvoidaccessibility of probe pads
Core Design Contradiction:
Volume of moving objectVSEase of operation

Solution Approach 1:

The patent introduces a new spatial dimension by routing the test signal path through the vertical TSV connection. Instead of accessing probe pads only from the chip surface plane, the signal traverses through the third dimension via TSVs to reach internal probe pads of lower chips, enabling testing in the stacked configuration.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

Bump pads serve as intermediary elements that facilitate the connection between external test equipment and internal probe pads. The bump pads exposed on the upper surface act as mediators, receiving test signals and transmitting them through TSVs to the internal probe pads, enabling indirect access for probing tests.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If probe pads are connected through TSVs to internal circuits, then electrical connection is achieved, but external access for testing is lost

Engineering Contradiction:
Improveelectrical connectionVSAvoidtesting accessibility
Core Design Contradiction:
ReliabilityVSDifficulty of detecting and measuring

Solution Approach 1:

The electrical connection path is segmented into distinct functional zones: bump pads for external interface, TSVs for vertical interconnection, and probe pads for internal circuit access. This segmentation allows each element to perform its specific function while maintaining overall system connectivity and testability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The bump pads serve multiple functions: they act as external electrical contacts for normal operation and simultaneously serve as access points for probing tests. This multi-functionality resolves the contradiction by enabling both reliable electrical connection and testing accessibility through the same structural element.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If multiple conductive layers are used to connect probe pads and bump pads, then electrical connectivity is improved, but manufacturing complexity increases

Engineering Contradiction:
Improveelectrical connectivityVSAvoidconductive layer structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines multiple conductive layers into an integrated conductive structure that provides both mechanical support and electrical connectivity. By merging the conductive functions into unified layers rather than separate discrete connections, the design achieves reliable electrical connectivity while reducing manufacturing complexity.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS10056354B2Multi-chip semiconductor apparatus
Publication Date: 2018.08.21 SK HYNIX INC
  • US10056354B2 patent drawing
  • US10056354B2 patent drawing
  • US10056354B2 patent drawing

AI summary

A multi-chip semiconductor apparatus includes a plurality of semiconductor chips stacked and packaged therein, wherein each of the semiconductor chips includes: a through-silicon via (TSV) formed through the semiconductor chip; a probe pad exposed to an outside of the semiconductor chip so as to enable a probing test; a bump pad exposed to the outside of the semiconductor chip and electrically connected to the TSV; and a conductive layer electrically connecting the probe pad and the bump pad inside the semiconductor chip.