Multi-Chip Semiconductor Weak Cell Address Storage Circuit
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Solution Overview
Problem
Semiconductor devices experience reduced operating speed due to the need for a separate refresh operation period, which reduces the time available for read/write operations and leads to data loss in memory cells over time.
Innovation Solution
A semiconductor device architecture that allows one chip to perform read/write operations while another chip performs a refresh operation simultaneously, using a weak cell address storage circuit and refresh control circuit to generate refresh addresses and manage data transmission across multiple chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate refresh operation period is allocated to recharge memory cells, then data integrity is maintained, but the time available for read/write operations is reduced, leading to reduced operating speed
Solution Approach 1:
The memory device is divided into multiple independent chips, each capable of autonomous operation. This segmentation allows different chips to perform different operations simultaneously - one chip performs read/write operations while another performs refresh operations, thereby resolving the contradiction between maintaining data integrity and preserving operating speed.
Solution Approach 2:
By enabling parallel operations across multiple chips, the system ensures that useful actions (read/write operations) continue without interruption while refresh operations are performed concurrently on other chips. This eliminates the periodic interruption caused by sequential refresh operations, maintaining continuous productivity.
2Reliability
If refresh operations are performed sequentially on each chip, then each chip maintains data integrity, but the overall operating speed of the semiconductor device is reduced due to time loss
Solution Approach 1:
The memory system is segmented into multiple chips that can operate independently and simultaneously. This allows refresh operations on one chip to occur at the same time as read/write operations on another chip, converting sequential time loss into parallel execution with no net time penalty.
Solution Approach 2:
The system transitions from a single-dimensional sequential operation model to a multi-dimensional parallel operation model. By adding the dimension of spatial parallelism across multiple chips, the system performs refresh operations in a different temporal dimension that does not interfere with read/write operations in the primary operational dimension.
Data Source
AI summary
A semiconductor device may include: a first chip, configured to receive a command and an address; and a second chip, configured to receive the command and the address. The first chip may include: a weak cell address storage circuit configured to store a weak cell address; a refresh control circuit configured to generate a refresh address based on the weak cell address, when the second chip is selected by a chip address; and a bank in which a refresh operation is performed by the refresh address.