Multi-Chip Stack Fabrication via Segmented Substrate Bonding
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Solution Overview
Problem
Existing methods for fabricating multi-chip stack packages face challenges in efficiently integrating logic and memory semiconductor devices within a single package using through-via electrodes, particularly in aligning and bonding substrates with varying horizontal widths, which affects the structural integrity and electrical connectivity.
Innovation Solution
A method involving the preparation of single-bodied lower and upper chip substrates, bonding unit package substrates, filling molding compounds, forming through-via electrodes, and separating the structures into unit chip stack packages, allowing for independent alignment and bonding of substrates with different widths without the need for a wafer supporting system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If unit package substrates with different horizontal widths are bonded onto single-bodied lower chip substrates, then alignment flexibility and adaptability are improved, but substrate damage risk and process complexity increase
Solution Approach 1:
The package substrate is divided into multiple unit package substrates with different horizontal widths, each capable of being independently aligned and bonded to the single-bodied lower chip substrate. This segmentation allows the system to adapt to different chip sizes and configurations while maintaining structural integrity through modular bonding units.
Solution Approach 2:
The single-bodied lower chip substrate and unit package substrates are prepared in advance with predetermined configurations before bonding. The lower chip substrate is fully processed with through-via electrodes and internal circuits before the unit package substrates are bonded onto it, ensuring that alignment requirements are established beforehand and reducing the risk of damage during subsequent processing.
2Device complexity
If single-bodied chip substrates are used without wafer supporting systems, then process complexity and manufacturing cost are reduced, but structural stability during bonding may be compromised
Solution Approach 1:
Multiple unit package substrates are bonded onto a single single-bodied lower chip substrate, merging multiple functional units into one integrated structure. This combining approach eliminates the need for separate wafer supporting systems for each unit, as the single-bodied substrate provides a unified stable base for all bonded units, reducing overall process complexity while maintaining structural integrity.
Solution Approach 2:
The single-bodied lower chip substrate serves its own structural support function without requiring external wafer supporting systems. The substrate's own mechanical properties and the bonding structure itself provide the necessary stability during the bonding process, making additional support systems redundant and simplifying the overall manufacturing process.
3Reliability
If through-via electrodes are formed in single-bodied lower chip substrates, then electrical connectivity between stacked chips is improved, but manufacturing precision requirements increase
Solution Approach 1:
Through-via electrodes are formed in the single-bodied lower chip substrate before bonding the unit package substrates. This preliminary formation of through-via electrodes ensures that precise alignment holes and conductive pathways are established in advance, allowing for high-precision electrical connectivity to be achieved before the substrate undergoes subsequent bonding processes that might otherwise compromise via alignment.
Solution Approach 2:
Multiple through-via electrodes are formed in a single continuous process across the entire single-bodied lower chip substrate, rather than processing each unit separately. This merging approach ensures uniform precision across all via electrodes, as they are created in the same manufacturing run under identical conditions, reducing variability and maintaining high electrical connectivity reliability.
Data Source
AI summary
Provided is a method of fabricating a multi-chip stack package. The method includes preparing single-bodied lower chips having a single-bodied lower chip substrate having a first surface and a second surface disposed opposite the first surface, bonding unit package substrates onto the first surface of the single-bodied lower chip substrate to form a single-bodied substrate-chip bonding structure, separating the single-bodied substrate-chip bonding structure into a plurality of unit substrate-chip bonding structures, preparing single-bodied upper chips having a single-bodied upper chip substrate, bonding the plurality of unit substrate-chip bonding structures onto a first surface of the single-bodied upper chip substrate to form a single-bodied semiconductor chip stack structure, and separating the single-bodied semiconductor chip stack structure into a plurality of unit semiconductor chip stack structures.