Multi-Chip Stack Package with Even Wire Lengths
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Solution Overview
Problem
Conventional wire-bonded multi-chip stack package structures face issues with signal transmission speed, time delay, and package dimension due to uneven lengths of bonding wires, leading to system malfunctions and data storage errors, while Redistribution Layer (RDL) solutions are costly and not widely adopted.
Innovation Solution
A multi-chip stack package structure where metal wires directly connect bumps on chips, using Through-Silicon-Vias (TSVs) to reduce package height and increase integration density, and employing conventional metal wires to replace RDL, ensuring even wire lengths for improved electrical performance and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional wire-bonded package structures are used to connect multiple chips, then the package can be manufactured with existing technology, but the bonding wires have uneven lengths causing lower signal transmission speed and time delay
Solution Approach 1:
The patent divides the connection structure into segments: chips are stacked vertically with bumps on their surfaces, and bonding wires connect corresponding bumps between adjacent chips. This segmentation allows each wire to have a controlled, relatively even length by connecting points at similar heights on adjacent chips, reducing signal transmission variations and improving reliability.
Solution Approach 2:
The patent transitions from a horizontal package layout to a vertical multi-chip stack configuration. By stacking chips vertically and connecting them through bumps and bonding wires in the vertical dimension, the patent achieves shorter wire lengths and more uniform wire length distribution, thereby improving signal transmission speed and reducing time delay.
2Quantity of substance
If the number of chips is increased to achieve higher memory capacity, then more functions can be integrated, but the package dimension and profile increase due to bonding wires with loop heights
Solution Approach 1:
The patent stacks multiple chips vertically in a compact arrangement, utilizing the vertical dimension to integrate more chips without proportionally increasing the package footprint. The bonding wires connect bumps on adjacent chips in the stack, and while loop heights contribute to package height, the vertical stacking approach allows for more efficient space utilization compared to horizontal expansion.
Solution Approach 2:
The patent implements a nested structure where multiple chips are stacked one on top of another, with each chip containing functional elements and bumps on its surface. This nesting approach allows multiple chips to occupy a compact vertical space, increasing memory capacity while controlling package dimensions.
3Speed
If RDL is employed to shorten wire connection paths, then electrical performance improves, but manufacturing cost increases significantly
Solution Approach 1:
The patent uses conventional, cost-effective bonding wires and standard chip bump structures instead of expensive RDL processes. By optimizing the wire bonding approach with even wire lengths and direct bump-to-bump connections, the patent achieves good electrical performance while maintaining low manufacturing costs associated with成熟 technologies.
Solution Approach 2:
The patent allows the bonding wires to directly connect bumps on adjacent chips without requiring additional RDL layers or complex redistribution structures. This self-service approach uses the existing bump structures on chips to create direct connections, eliminating the need for costly RDL manufacturing processes while maintaining short connection paths.
Data Source
AI summary
A multi-chip stack package structure comprises a substrate, which has a chip placement area defined on its upper surface and a plurality of contacts disposed outside the chip placement area; a first chip is disposed in the chip placement area with the rear surface, a plurality of first pads being disposed on the active surface and a plurality of first bumps each being formed on one of the first pads; a plurality of metal wires connect the first bumps to the contacts; a second chip with a plurality of second pads being disposed on the active surface and a plurality of second bumps each being formed on one of the second pads, the second chip being mounted to the first chip with its active surface facing the active surface of the first chip, wherein the second bumps correspondingly connect the metal wires and the first bumps respectively.