Multi-Chip Storage Interconnect With Stacked Conductive Layers
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Solution Overview
Problem
Existing semiconductor storage devices face challenges in effectively connecting conductive films between multiple chips, leading to inefficiencies in power transmission and potential reliability issues during manufacturing and mounting.
Innovation Solution
A semiconductor storage device configuration that includes multiple chips with stacked conductive layers and plugs, allowing for parallel connection of conductive films to reduce resistance and thickness, while maintaining efficient power transmission and improving mounting reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive films are used to connect multiple chips, then electrical connection is achieved, but resistance is high and reliability is poor due to peeling and voids
Solution Approach 1:
The patent transitions from planar conductive films to three-dimensional stacked conductive layers. Multiple conductive layers are stacked in the vertical direction with plugs connecting them, creating a dimensional change that reduces resistance and improves reliability without increasing lateral space occupation.
Solution Approach 2:
The patent employs composite conductive structures combining multiple materials (e.g., Cu/W, Cu/Ta, Cu/Mo) in the stacked layers. Each material serves specific functions: Cu provides low resistance, while W/Ta/Mo provide barrier and adhesion properties, creating a composite structure that optimizes both electrical performance and mechanical reliability.
2Loss of energy
If conductive film thickness is increased to reduce resistance, then power transmission improves, but manufacturing complexity and void formation increase
Solution Approach 1:
The patent divides the conductive path into multiple thin stacked layers instead of using a single thick film. Each layer has optimized thickness (e.g., Cu layer 50-200nm, barrier layer 5-20nm), making each layer manufacturable with standard processes while achieving low overall resistance through the stacked configuration.
Solution Approach 2:
By stacking conductive layers vertically, the patent achieves equivalent or superior electrical performance to thick films without increasing lateral dimensions. The vertical stacking allows multiple thin layers to be manufactured using standard thin-film deposition processes, avoiding the manufacturing difficulties of thick single-layer films.
3Ease of manufacture
If single-layer conductive films are used, then manufacturing is simpler, but resistance is high and peeling occurs
Solution Approach 1:
The patent creates composite conductive structures with multiple materials stacked together (e.g., Cu barrier layer + Cu conductive layer). The barrier/adhesion layers provide strong bonding to underlying structures, preventing peeling, while the Cu layers provide low resistance. This composite approach maintains manufacturing feasibility through sequential deposition processes.
Solution Approach 2:
The patent moves from a single-layer planar structure to a multi-layer stacked structure. Each layer can be optimized for its specific function (adhesion, conduction, barrier) and manufactured using standard sequential deposition processes, achieving both reliability and manufacturing ease.
4Device complexity
If conductive films are made thinner to reduce complexity, then manufacturing improves, but resistance increases and power transmission deteriorates
Solution Approach 1:
The patent segments the conductive path into multiple thin layers, each with optimized thickness for manufacturability. The cumulative effect of multiple thin layers with low-resistance materials (Cu) and good adhesion layers achieves low overall resistance while maintaining thin individual layer thicknesses that are easy to manufacture.
Solution Approach 2:
By using composite materials with low-resistance conductive layers (Cu) stacked with thin barrier/adhesion layers (W, Ta, Mo), the patent achieves excellent power transmission. The conductive layers provide low resistance pathways while the barrier layers are thin enough not to significantly increase resistance, optimizing the balance between thickness and electrical performance.
Data Source
AI summary
According to one embodiment, a semiconductor storage device includes a first chip, a second chip, and a third chip. In the third chip, a first conductive film is above a first stacked body. The first conductive film extends across the first stacked body when viewed from a stacking direction. A first plug extends in the stacking direction and connects the first conductive film and a second conductive film. The first electrode is connected to the second conductive film. In the second chip, a third conductive film is above a second stacked body. A second plug extends in the stacking direction and connects the third conductive film and the fourth conductive film. The second electrode is connected to the fourth conductive film. The first chip has a first wiring structure therein. The first wiring structure is connected to the second electrode.