Multi-chip Structure Segments Switch SOC and SerDes Chips
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Solution Overview
Problem
Conventional switch system on chip (SOC) faces challenges in optimizing power dissipation and supporting multiple standards for serializer/deserializer (SerDes) circuits, particularly due to limitations in advanced CMOS processes and low supply voltage for high-speed operations.
Innovation Solution
A multi-chip structure comprising a switch SOC and multiple SerDes chips connected via inter-chip interfaces, allowing each component to be designed and manufactured independently to optimize performance and support various Ethernet standards, with flexibility in semiconductor processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If SerDes circuits are integrated within the switch SOC to support multi-standards, then versatility is improved, but power dissipation cannot be optimized and overhead increases
Solution Approach 1:
The patent divides the switch system into separate components: the switch SOC and external SerDes circuits. This segmentation allows the SerDes circuits to be independently optimized for specific standards (NRZ, PAM4, etc.) while the switch SOC maintains its advanced CMOS process optimization, thereby reducing overall power dissipation while supporting multi-standards through modular configuration.
2Device complexity
If SerDes circuits are integrated within the switch SOC, then device complexity is reduced, but manufacturing precision suffers due to process limitations
Solution Approach 1:
The patent separates the switch SOC from the SerDes circuits, allowing each to be manufactured using the most appropriate process. The switch SOC can be produced using advanced CMOS processes (e.g., 10nm, 7nm) for high integration density, while SerDes circuits can be manufactured using processes optimized for high-speed signal integrity and wide dynamic range operation, thereby improving manufacturing precision for each component.
3Use of energy by moving object
If the switch SOC uses low supply voltage process for power efficiency, then power consumption is reduced, but SerDes circuits cannot operate in wide dynamic range
Solution Approach 1:
The patent separates the low-power switch SOC from the SerDes circuits that require wide dynamic range operation. The switch SOC can operate at low supply voltages (e.g., 0.75V at 10nm process) for power efficiency, while external SerDes circuits can be supplied with higher voltages needed for wide dynamic range operation, thus resolving the contradiction between power consumption and dynamic range capability.
4Ease of manufacture
If advanced CMOS process is used for switch SOC, then manufacturing cost is optimized, but SerDes circuits cannot achieve high-speed performance
Solution Approach 1:
The patent divides the system so that the switch SOC is manufactured using cost-effective advanced CMOS processes, while SerDes circuits are implemented using processes specifically optimized for high-speed performance. This segmentation allows each component to be manufactured with the most appropriate process technology, achieving both cost optimization and high-speed performance.
Data Source
AI summary
A multi-chip structure comprises a switch system on chip (switch SOC), a plurality of serializer/deserializer (SerDes) chips positioned around the switch SOC, and a plurality of inter-chip interfaces for connecting the switch SOC to the plurality of SerDes chips, respectively.