Multi-Chip Package Structure for Thinner High-Density Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in semiconductor device manufacturing is to reduce the thickness of chip package structures with multiple chips while maintaining their functionality and reliability, as conventional methods struggle to efficiently integrate and package multiple chips in a compact form.
Innovation Solution
The process involves forming conductive pillars and bumps using a seed layer and mask layer, followed by plating and thinning, to create a chip package structure where the molding material layer supports the substrate during grinding, allowing for further thinning and reducing the overall thickness. Conductive bumps are formed over the pillars, and the structure is bonded to a wiring substrate with an underfill layer, increasing the number density of bumps for improved signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple chips are integrated in a chip package structure, then functionality is improved, but thickness increases
Solution Approach 1:
The patent transitions from vertical stacking to lateral integration by arranging multiple chip structures side-by-side on the same substrate plane. This dimensional change allows multiple functional chips to be packaged without increasing thickness, as they occupy horizontal space rather than vertical space.
Solution Approach 2:
The package structure is segmented into multiple independent chip structures, each with its own substrate and circuit components, arranged laterally. This segmentation enables functional diversity while maintaining a thin profile by distributing chips across the substrate area rather than stacking them vertically.
2Reliability
If the number of conductive bumps is increased, then signal transmission efficiency is improved, but manufacturing complexity increases
Solution Approach 1:
Conductive bumps are formed on the chip structures before bonding to the interconnect layer. This preliminary formation allows for precise control of bump placement and dimensions, enabling high bump density without proportionally increasing manufacturing complexity, as the bumps are created in a controlled sequence rather than attempting to align multiple complex components simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a thinner chip package structure with enhanced signal transmission efficiency and improved performance by increasing the number density of conductive bumps, while also reducing thermal stress and damage during processing.
Implementation Method 1
forming conductive pillars and bumps using a seed layer and mask layer, followed by plating
Data Source
AI summary
A chip package structure is provided. The chip package structure includes a first chip structure including a substrate and an interconnect layer over the substrate. The chip package structure includes a second chip structure over the interconnect layer. The chip package structure includes a first conductive bump connected between the interconnect layer and the second chip structure. The chip package structure includes a conductive pillar over the interconnect layer. The chip package structure includes a molding layer over the interconnect layer and surrounding the second chip structure, the first conductive bump, and the conductive pillar. The chip package structure includes a second conductive bump over a first surface of the conductive pillar. The first surface faces away from the first chip structure.