Multi-chip Touch Architecture Scalability via Parallel ASIC Processing
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Solution Overview
Problem
Existing touch controller architectures are unsuitable for scalability, as they fail to efficiently process touch data across varying sizes of touch screens, leading to inefficiencies in touch sensing and processing.
Innovation Solution
A multi-chip touch architecture is introduced, featuring touch controller ASICs and switching circuits that can be scaled based on the size of the touch sensor panel, with daisy chain or ring configurations for data transfer, and hardware accelerators for enhanced processing speeds, including a scan sequencer for optimized scanning operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single touch controller architecture is used for all screen sizes, then device complexity is reduced, but scalability and processing efficiency deteriorate
Solution Approach 1:
The touch controller is divided into multiple independent ASIC chips that can be configured in different numbers and arrangements based on screen size. Each chip handles a specific portion of the touch sensor panel, allowing the system to scale from small to large displays without redesigning the entire controller architecture.
Solution Approach 2:
The touch controller ASICs are designed with universal interfaces and standardized communication protocols that allow them to function in various configurations. The same basic chip design can serve different screen sizes and panel types through flexible inter-chip connectivity arrangements.
2Adaptability or versatility
If touch controller ASICs are distributed across multiple chips, then scalability improves, but data transfer complexity increases
Solution Approach 1:
Multiple touch controller ASICs are merged into a cohesive system through standardized interfaces and synchronized operation. The chips work together as a unified controller, sharing the burden of data processing and coordination through defined communication protocols.
Solution Approach 2:
A centralized coordination mechanism acts as an intermediary between the distributed ASICs, managing data transfer coordination and synchronization. This mediator ensures efficient data exchange without requiring complex peer-to-peer negotiation between chips.
3Productivity
If parallel processing is implemented across multiple ASICs, then processing speed improves, but system complexity increases
Solution Approach 1:
The touch data processing task is segmented and distributed across multiple ASICs, with each chip handling specific portions of the touch sensor panel simultaneously. This division of labor enables parallel processing that increases overall throughput while keeping individual chip complexity manageable.
Solution Approach 2:
The parallel processing architecture maintains continuous operation across all ASICs, with each chip continuously scanning and processing touch data from its assigned panel region. This continuous useful action eliminates idle time and maximizes processing throughput.
Data Source
AI summary
A multi-chip touch architecture for scalability can include one or more touch controller application specific integrated circuits (ASICs), and one or more switching circuits coupled between the one or more touch controller ASICs and the touch sensor panel. The number of touch controller ASICs and switching circuits can be scaled based on the size of the touch sensor panel. The touch controller ASICs can include an interface for data transfer between the touch controller ASICs to allow for parallel processing of an image of touch by more than one touch controller ASIC. The touch controller ASIC can also include a memory directly accessible by more than one processing circuit (e.g., hardware accelerators), and circuitry to dynamically adjust the coupling between portions (e.g., banks) of memory and inputs of the one or more processing circuits to minimize data transfer and improve processing speeds.