Multi-chip Wafer Level Package Stacked Die Interconnection
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving smaller form factors and reducing parasitic losses in traditional multi-chip devices, as they rely on wire bonding for interconnection, which results in longer signal paths and increased power consumption.
Innovation Solution
The implementation of multi-chip wafer level package technology, where semiconductor dies are stacked using micro bumps and through-silicon vias, allowing for shorter signal paths and reduced parasitic losses, along with the use of photo-sensitive material layers and under bump metallization structures for efficient electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If wire bonding is used for interconnection in traditional multi-chip devices, then ease of manufacture is improved, but signal path length increases and parasitic losses increase
Solution Approach 1:
The patent transitions from planar wire bonding to three-dimensional vertical interconnection through micro bumps and through-silicon vias. This dimensional change allows signals to travel vertically between stacked semiconductor dies rather than laterally across a substrate, significantly reducing signal path length and associated parasitic losses while maintaining manufacturing feasibility through established bump bonding and via formation processes
2Device complexity
If traditional multi-chip packaging is used, then device complexity is reduced, but form factor cannot be reduced further
Solution Approach 1:
The patent implements a stacked architecture where multiple semiconductor dies are vertically nested one on top of another, similar to nested dolls. Each die contains active circuits and is interconnected through micro bumps and through-silicon vias, allowing high-density integration of multiple functional blocks within a compact vertical footprint, thereby reducing the overall form factor while managing device complexity through modular design
3Productivity
If more semiconductor dies are stacked together, then density increases and performance increases, but fabrication complexity increases
Solution Approach 1:
The patent employs preliminary action by forming through-silicon vias and applying under bump metallization structures to semiconductor dies before the actual stacking process. This pre-preparation of interconnection structures on each die individually simplifies the subsequent assembly process, allowing high-density stacking to be achieved while controlling fabrication complexity through standardized pre-processing steps that can be performed using established semiconductor manufacturing techniques
Data Source
AI summary
A multi-chip wafer level package comprises three stacked semiconductor dies. A first semiconductor die is embedded in a first photo-sensitive material layer. A second semiconductor die is stacked on top of the first semiconductor die wherein the second semiconductor die is face-to-face coupled to the first semiconductor die. A third semiconductor die is back-to-back attached to the second semiconductor die. Both the second semiconductor die and the third semiconductor die are embedded in a second photo-sensitive material layer. The multi-chip wafer level package further comprises a plurality of through assembly vias formed in the first photo-sensitive material layer and the second photo-sensitive material layer.