Multi-Clock Circuit Generation via Compiler Parallelism Detection
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Solution Overview
Problem
Existing circuit design technologies face challenges in efficiently generating hardware that utilizes multiple clock frequencies, leading to limitations in clock speed and throughput, particularly when interfacing different hardware blocks with varying processing capabilities.
Innovation Solution
A compiler system is developed to automatically generate hardware description data that allows for the use of multiple clock frequencies by detecting execution parallelism in program code and optimizing the number and configuration of functional blocks, enabling interface circuitry to operate at one frequency while functional components operate at a higher frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If interface circuitry is run at a lower clock frequency to meet throughput requirements, then data transfer reliability is improved, but functional components cannot operate at their optimal processing speed
Solution Approach 1:
The system divides the hardware into separate clock domains: interface circuitry operates at a first clock frequency while functional components operate at a second, higher clock frequency. This segmentation allows each part to operate independently at its optimal speed without being constrained by the other.
Solution Approach 2:
A multi-clock FIFO buffer is introduced as an intermediary between the interface circuitry and functional components. This buffer decouples the two clock domains, allowing data to be transferred reliably at the interface clock frequency while functional components process data at their higher operating frequency.
2Manufacturing precision
If manual generation of multi-clock instructions is performed, then precise clock frequency control is achieved, but design time and complexity increase significantly
Solution Approach 1:
The system automatically detects execution parallelism in the program code and generates appropriate multi-clock instructions without requiring manual intervention. The compiler analyzes the code structure and autonomously determines the optimal clock frequency configuration and functional block instantiation.
Solution Approach 2:
The compiler transforms the program code by introducing clock frequency parameters and generating instructions that specify different clock rates for different hardware components. This automatic parameter transformation enables precise multi-clock control while eliminating manual design effort.
3Productivity
If functional blocks are increased in number to meet processing requirements, then throughput is improved, but hardware cost and device complexity increase
Solution Approach 1:
Functional components operate continuously at a higher clock frequency, processing multiple data items within the time frame of a single interface clock cycle. This continuous high-speed operation achieves high throughput without requiring multiple functional blocks.
Solution Approach 2:
The system transitions from increasing the number of functional blocks (spatial dimension) to increasing the clock frequency (temporal dimension) to achieve higher throughput. By operating faster in time rather than adding more components in space, the system maintains simplicity while improving performance.
Data Source
AI summary
Hardware may be created with different clock speeds used for different components of the system. Clock and throughput requirements on the interface circuitry of hardware components may set limits which are lower requirements for functional components. It may be advantageous to use more or fewer of some functional blocks or interface circuits in order to reduce cost, increase performance or reliability, reduce the requirements for additional parts, or other beneficial factors. Accordingly, it may be advantageous to generate hardware utilizing more than a single clock frequency. Generating instructions which indicate different clock frequencies for separate components may be difficult or time consuming; generating these instructions automatically may provide significant benefits in time savings, increased productivity, increased performance of hardware, or other benefits.