Multi-Clock Domain Testing via Sequential Capture Pulses
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Solution Overview
Problem
Automatic Test Pattern Generation (ATPG) tools face challenges in testing multi-clock domains of integrated circuits, leading to excessive switching activity beyond the specified power budget, inaccurate reporting of switching activity for individual clock domains, and reduced test coverage due to limited flexibility in choosing test patterns.
Innovation Solution
The method involves providing capture pulses at specific frequencies to each clock domain sequentially, using a scan enable signal to differentiate between shift and capture modes, and establishing a timing relationship between clock controllers to accurately predict switching activity and maintain power budgets for each domain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If ATPG tools generate test patterns to achieve maximum test coverage, then test coverage is improved, but switching activity exceeds the specified power budget
Solution Approach 1:
The patent segments the testing process by separating different clock domains and testing them independently. Each clock domain is tested with dedicated capture pulses at its specific frequency, allowing test patterns to be optimized for each domain's coverage requirements without causing excessive switching activity across the entire IC. This segmentation enables maximum test coverage while controlling overall power consumption.
2Device complexity
If ATPG tools assign a combined power budget for all clock domains, then power budget control is simplified, but flexibility in choosing test patterns is reduced and test coverage decreases
Solution Approach 1:
The patent assigns individual power budgets to each clock domain rather than using a combined power budget. This segmentation allows independent control of switching activity for each domain, providing flexibility in test pattern selection and maximizing test coverage for each domain while maintaining overall power budget compliance.
Solution Approach 2:
The patent applies local quality by tailoring test patterns and power budget constraints to each specific clock domain's requirements. Each domain receives customized test patterns optimized for its architecture and fault detection needs, rather than using a one-size-fits-all approach, thereby improving test coverage while managing power consumption locally.
3Productivity
If ATPG tools provide capture pulses to multiple clock domains simultaneously, then testing efficiency is improved, but inaccurate switching activity reporting occurs for individual domains
Solution Approach 1:
The patent segments the capture pulse distribution by providing pulses to clock domains sequentially rather than simultaneously. Each domain receives capture pulses at its specific frequency in a dedicated time window, controlled by sequential scan enable signals. This timing separation ensures that switching activity is accurately measured and reported for each individual domain without interference from other domains, while maintaining high testing efficiency through sequential processing.
Data Source
AI summary
A system for testing multi-clock domains in an integrated circuit (IC) includes a plurality of clock sources coupled to a plurality of clock controllers. Each of the clock sources generates a fast clock associated with one of the multi-clock domains. Each of the clock controllers is configured to provide capture pulses to test one clock domain. The capture pulses provided to a clock domain are at a frequency of a fast clock associated with the clock domain. The clock controllers operate sequentially to provide the capture pulses to test the clock domains.