Multi-Clock Pipeline Digital Filter for Throughput-Area Tradeoffs
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Solution Overview
Problem
Digital signal processing (DSP) technologies face challenges in achieving precision and robustness due to high silicon area occupation, leading to performance limitations and increased costs, particularly in applications requiring multiple frequency operations and complex digital filters like those in metrology.
Innovation Solution
A digital filter with a pipeline structure is implemented using multiple clock domains and up-sampling/down-sampling buffers, along with a phase generator to align processing modules with input samples, allowing for efficient operation across different frequencies and flexible reuse of processing blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple copies of digital operators are instantiated to maintain throughput, then processing performance is improved, but silicon area occupation increases
Solution Approach 1:
Multiple processing structures are merged into a single shared processing structure that operates in different clock domains. The processing modules are time-multiplexed across multiple clock domains, allowing one physical structure to serve multiple functional roles that would traditionally require separate copies, thereby reducing silicon area while maintaining throughput capability
Solution Approach 2:
The processing structure dynamically switches between different clock domains based on the operational requirements of different processing stages. By making the clock domain assignment dynamic rather than static, the system can reuse the same processing modules across different time slots and clock frequencies, eliminating the need for dedicated hardware copies for each frequency requirement
2Area of stationary object
If processing modules are re-used across clock domains, then silicon area is reduced, but synchronization complexity increases
Solution Approach 1:
The system is segmented into distinct clock domains, each with its own clock signal and timing characteristics. By dividing the processing pipeline into separate clock domain segments, the synchronization complexity is localized to the boundaries between domains rather than affecting the entire system, making it more manageable through dedicated phase generators at each domain interface
Solution Approach 2:
Phase generators act as intermediary components between different clock domains, translating and aligning timing signals across domain boundaries. These intermediaries handle the complex synchronization requirements by generating appropriate phase-aligned clock signals, isolating the complexity from the main processing logic and enabling seamless operation across multiple clock domains
3Adaptability or versatility
If processing structures operate at different clock frequencies, then frequency adaptability is improved, but signal synchronization between domains becomes difficult
Solution Approach 1:
The system changes the clock frequency parameter dynamically based on the processing stage requirements. Each clock domain operates at an optimized frequency for its specific processing tasks, and the phase generators ensure that signal transitions between domains maintain proper timing relationships despite frequency differences, thereby preserving synchronization reliability across varying frequencies
Data Source
AI summary
A digital filter with a pipeline structure includes processing structures timed by respective clock signals. Each processing structure in turn is formed by a number of processing modules for processing input samples. A phase generator aligns the processing modules with the input samples so that each input sample is processed by a respective one of the processing modules. An up-sampling buffer and a down-sampling buffer are used when the processing structures operate at different clock frequencies (thus implementing different clock domains) so as to convert signal samples between the clock domains for processing in the processing structures.