Multi-Clock IC Architecture Using One Crystal Oscillator and PLL
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Solution Overview
Problem
Existing integrated circuits require multiple crystal oscillator circuits to generate different clock signals, leading to increased cost and space occupancy on printed circuit boards.
Innovation Solution
An integrated circuit with multiple clock signals is designed, incorporating a single crystal oscillator circuit, a phase-locked loop circuit, and function circuits to generate and operate based on multiple clock signals, reducing the need for multiple oscillator circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple crystal oscillator circuits are used to generate different clock signals, then the reliability of clock signal generation is improved, but the cost and space occupancy on printed circuit boards increase
Solution Approach 1:
The patent merges multiple clock signal generation functions into a single crystal oscillator circuit by integrating a phase-locked loop (PLL) circuit. The PLL circuit receives the output signal from the crystal oscillator and generates multiple different clock signals through frequency division and phase locking mechanisms, eliminating the need for multiple separate crystal oscillator circuits on the printed circuit board.
Solution Approach 2:
The crystal oscillator circuit is designed with multi-functionality by combining it with the PLL circuit. This integrated system can generate multiple different clock signals simultaneously to drive different functional circuits within the device, making a single circuit perform the work of multiple separate oscillators while reducing overall component count and board space.
2Adaptability or versatility
If multiple crystal oscillator circuits are disposed on the SoC, then each circuit can operate independently with its own clock signal, but the device complexity and manufacturing cost increase
Solution Approach 1:
The patent applies segmentation by dividing the clock signal generation function into two independent modules: a crystal oscillator circuit that generates a base clock signal, and a PLL circuit that processes this signal to generate multiple different clock signals. This modular segmentation allows different functional circuits to receive appropriately divided clock signals while maintaining operational independence without requiring multiple complete oscillator circuits.
Solution Approach 2:
The PLL circuit serves as an intermediary between the single crystal oscillator and multiple functional circuits. It receives the master clock signal from the oscillator and transforms it into multiple different clock signals through frequency division and phase locking, mediating the clock distribution needs of various independent circuits without requiring each circuit to have its own oscillator.
Data Source
AI summary
An integrated circuit with multiple clock signals includes a crystal oscillator circuit, a first function circuit, a phase-locked loop circuit, and a second function circuit. The crystal oscillator circuit is configured to generate a first clock signal. The first function circuit is configured to receive the first clock signal and operates according to the first clock signal. The phase-locked loop circuit is configured to generate a second clock signal according to the first clock signal. The second function circuit is configured to receive the second clock signal and operates according to the second clock signal.