Multi-Clock Generator Architecture for Low-Latency Frequency Scaling
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Solution Overview
Problem
Conventional clock management systems in computer systems face latency issues when adjusting system clock frequencies, particularly in systems with multiple phase-locked loops (PLLs), which can lead to prolonged re-locking times and synchronization challenges.
Innovation Solution
The implementation of a programmable clock generator system that uses multiple clock generators to independently adjust clock frequencies without modifying the PLL's frequency, employing pulse skipping techniques to achieve a wide frequency range and reduce latency, allowing for efficient frequency changes in modern microprocessor systems with multiple clock domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the system uses a single PLL to provide clock signals, then device complexity is reduced, but latency increases due to PLL re-locking time when adjusting frequency
Solution Approach 1:
The system divides the clock generation function into two independent parts: the PLL maintains a fixed high-frequency reference clock, while separate clock generators in each clock domain independently adjust their output frequencies using pulse skipping techniques. This segmentation eliminates the need for PLL re-locking when changing frequencies.
Solution Approach 2:
Clock generators act as intermediary components between the fixed PLL reference clock and the variable frequency requirements of different clock domains. These intermediaries use pulse skipping to transform the stable reference clock into domain-specific frequencies without requiring PLL frequency changes.
2Adaptability or versatility
If the system uses multiple PLLs to serve different clock domains, then frequency adjustment flexibility is improved, but device complexity and synchronization difficulty increase
Solution Approach 1:
A single PLL serves all clock domains by providing a stable reference clock, while multiple clock generators handle domain-specific frequency adjustments. This multi-functionality approach allows one PLL to support multiple frequencies across different domains through the pulse skipping mechanism.
Solution Approach 2:
The system introduces dynamic frequency adjustment capability at the clock generator level rather than requiring dynamic PLL reconfiguration. Each clock domain can independently and dynamically change its frequency by adjusting pulse skipping patterns, providing flexibility without additional PLLs.
3Use of energy by stationary object
If the system adjusts PLL frequency for power management, then power savings are achieved, but re-locking latency of several hundred microseconds occurs
Solution Approach 1:
The PLL maintains a fixed reference frequency that is already optimized for power efficiency. Clock generators pre-load frequency division ratios and use pulse skipping to achieve frequency changes without triggering PLL re-locking, thus avoiding the time penalty while maintaining power management capabilities.
4Productivity
If the system uses pulse skipping techniques in clock generators, then frequency range and adjustment speed are improved, but clock signal quality may be affected
Solution Approach 1:
Pulse skipping is implemented as a periodic modulation technique where clock pulses are selectively removed in a regular pattern. This periodic action allows frequency adjustment while maintaining clock signal integrity, as the skipping follows a predictable sequence that preserves timing relationships.
Data Source
AI summary
A clock generator system (400) includes a phase locked loop (PLL) (402), a first clock generator (404), and a second clock generator (406). The PLL (402) includes a first output configured to provide a first clock signal at a first frequency and a second output configured to provide a second clock signal at the first frequency. The second clock signal is out-of-phase with the first clock signal. An output of the first clock generator (404) is configured to provide a first generated clock signal whose effective frequency is based on both the first and second clock signals and a first mode signal. An output of the second clock generator (406) is configured to provide a second generated clock signal whose effective frequency is based on both the first and second clock signals and a second mode signal.