Multi-Clock Phase Alignment During Selective Clock Gating
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Solution Overview
Problem
Existing clock management circuits in portable electronic devices lose phase synchronization between multiple clocks when one or more clock signals are disabled and later enabled, leading to sub-optimal power management, reduced battery life, and increased instantaneous current and heat dissipation.
Innovation Solution
A clock generator circuit that divides a reference clock signal by at least a factor of two to generate a master clock signal, synchronizing each output clock signal to a synchronization edge of the master clock signal to maintain predetermined phase relationships, ensuring that disabled clock signals are enabled in a way that preserves their relative phase relationships with other clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If clock signals are selectively disabled to save power, then power consumption is reduced, but phase synchronization between clocks is lost when clocks are re-enabled
Solution Approach 1:
A synchronization circuit acts as an intermediary between the disabled clock signal and the master clock signal. When a clock is re-enabled, the synchronization circuit captures the current phase of the master clock and uses it to properly phase-align the re-enabled clock, preventing phase synchronization loss while maintaining power savings from selective clock disabling
Solution Approach 2:
The synchronization circuit performs preliminary phase capture and alignment actions before the re-enabled clock signal is fully operational. By capturing the master clock phase in advance and preparing the appropriate synchronization signal, the system ensures phase continuity is restored before the clock begins driving circuitry, preventing transient phase mismatches
2Productivity
If multiple clocks are enabled simultaneously, then circuit functionality is complete, but instantaneous current surges and heat dissipation increase
Solution Approach 1:
The system implements periodic staggering of clock enablement by maintaining predetermined phase relationships between multiple clocks. Clocks are enabled at different phases rather than simultaneously, distributing the instantaneous current demand over time periods while ensuring all required circuit functions remain operational through coordinated clock phasing
3Adaptability or versatility
If clock phase relationships are not maintained during enable/disable transitions, then power management flexibility is improved, but battery life is reduced due to current surges
Solution Approach 1:
The synchronization circuit continuously monitors the phase relationship between the master clock and re-enabled clocks, using feedback from the master clock signal to dynamically adjust and maintain proper phase alignment. This feedback mechanism ensures that power management operations maintain optimal phase relationships, preventing current surges that would reduce battery life while preserving flexibility in clock enablement strategies
Data Source
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AI summary
A clock generation circuit is operative to disable and enable a plurality of output clock signals while maintaining predetermined phase relationships between the clock signals. A reference clock signal is divided by a factor of at least two, to generate a master clock signal. A plurality of phase circuits, each independently enabled, generates a plurality of output clock signals by dividing the reference clock signal. The output clock signals have predetermined phase relationships relative to each other. Each phase circuit is enabled synchronously to a synchronization edge of the master clock signal. A synchronization circuit associated with each phase circuit ensures synchronization with the master clock signal by outputting a phase circuit enable signal only upon the conditions of a clock enable signal associated with the output clock being asserted and the receipt of a predetermined number of master clock signal synchronizing edges.