Multi-Clock Domain Event Signal Sampling for Timing Precision
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Solution Overview
Problem
Existing systems face challenges in synchronizing event signals across multiple clock domains with different clocking signals, leading to inefficiencies in sampling and analysis, particularly in achieving high-frequency and high-precision timing synchronization.
Innovation Solution
A system and method where an event signal is sampled using multiple candidate clock domains, with the sampled data being fed to a master clock domain for analysis, allowing for precise identification of parameters like maxima, minima, and threshold crossings, and enabling synchronization of timing across different clock domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single clock domain is used for sampling event signals, then the device complexity is reduced, but the measurement precision and timing resolution are insufficient
Solution Approach 1:
The system divides the sampling function into multiple independent clock domains, each with its own clock signal and sampling circuit. This segmentation allows each domain to operate independently at optimal frequencies, improving overall timing resolution without requiring a single complex high-frequency clock system.
Solution Approach 2:
The patent transitions from a single-dimension (single clock frequency) sampling approach to a multi-dimensional approach by introducing multiple clock domains with different frequencies and phases. This dimensional expansion in the frequency domain enables higher effective sampling rates and better timing precision through interpolation algorithms.
2Measurement precision
If multiple clock domains with different clocking signals are used, then the timing synchronization precision is improved, but the device complexity increases
Solution Approach 1:
The patent introduces a master clock domain that acts as an intermediary to coordinate the multiple candidate clock domains. The master clock provides reference timing signals and collects data from all candidate domains, managing the complexity of inter-domain synchronization while enabling high-precision timing measurements.
Solution Approach 2:
The system dynamically selects and switches between different clock domains based on measured performance parameters such as jitter, phase noise, and synchronization accuracy. This parameter-based selection allows the system to adapt to different operating conditions and maintain optimal timing precision without requiring all domains to operate at maximum complexity simultaneously.
3Productivity
If high-frequency clocking signals are used, then the sampling rate is increased, but the loss of information due to timing jitter increases
Solution Approach 1:
The patent combines measurements from multiple clock domains with different frequency characteristics into a unified timing measurement. By merging data from domains that are less susceptible to specific types of jitter, the system achieves high effective sampling rates while preserving timing information accuracy through complementary measurement fusion.
Solution Approach 2:
The system implements feedback mechanisms where timing measurement results are used to adjust and optimize the selection and operation of candidate clock domains. This feedback loop allows the system to identify and compensate for jitter patterns, maintaining high sampling rates while minimizing information loss through adaptive clock domain management.
Data Source
Figure 1
AI summary
A system and a method of sampling an event signal using multiple clocking signals each provided in a separate candidate clock domain each of which also receives points in time from a master clock. From each candidate clock domain, clocked by the individual clocking signals, pairs of a received point in time and event signal value are fed to a master clock domain. In the master clock domain, the values of the event signal may be determined over time as a function of master clock time. This may be used for synchronizing operation in the master clock domain of e.g. packet time stamping with an overall time defined by the event signal. Using multiple clocking signals for the sampling, a much more precise sampling of the event signal is facilitated.