Multi-column decoder for non-consecutive memory access
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Solution Overview
Problem
Conventional memory devices are inefficient in accessing non-consecutive memory cells, leading to performance and power consumption issues when handling multi-dimensional array data, which requires additional costs to switch between memory mapping schemes.
Innovation Solution
A memory device with a multi-column decoder and a gating circuit that selects and accesses multiple non-consecutive columns simultaneously, using a multi-column selection signal and data mask signal to improve data write/read operations, allowing for efficient access of inconsecutive memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional memory devices access only consecutive memory cells, then the memory access structure is simple, but the performance and efficiency deteriorate when handling multi-dimensional array data with locality requirements
Solution Approach 1:
The memory cell array is divided into multiple banks, with each bank containing multiple columns. The column decoder is segmented to selectively decode different column groups independently. This segmentation allows the system to access non-consecutive columns across different banks simultaneously, improving productivity for multi-dimensional array data while maintaining a manageable device structure through modular organization.
Solution Approach 2:
The patent introduces a new dimension of memory access by enabling selection of multiple column groups along the column address dimension. Instead of accessing only consecutive columns in a single sequence, the system can now access columns from different banks and different column groups in parallel, effectively adding a bank-selection dimension to the traditional row-column access model. This resolves the contradiction by providing flexible non-consecutive access without fundamentally redesigning the entire memory structure.
2Adaptability or versatility
If memory devices switch between raster scheme and tile scheme, then adaptability to different data patterns improves, but additional costs and complexity are required
Solution Approach 1:
The column decoder is designed with multi-functionality to support both raster scheme and tile scheme operations within a single unified structure. By incorporating bank selection signals and column group selection signals, the same decoder hardware can adapt to different data access patterns without requiring separate switching mechanisms. This universal design improves adaptability while avoiding the additional complexity of multiple dedicated decoders or switching circuits.
Solution Approach 2:
The memory access structure employs dynamic selection of column groups and banks based on real-time access patterns. The column decoder can dynamically activate different column groups (e.g., even columns or odd columns) depending on the operation requirements. This dynamic capability allows the system to adapt to both raster and tile schemes flexibly, improving versatility without requiring static pre-configured switching mechanisms that would increase device complexity.
3Productivity
If only consecutive columns are accessed at a time, then the decoding circuit is simple, but the ability to handle multi-dimensional locality deteriorates
Solution Approach 1:
The column address space is segmented into multiple column groups, with each group independently decodable. The column decoder receives a column address and column group selection signal, then activates the corresponding column group. This segmentation enables the decoding circuit to handle non-consecutive column access by selecting specific column groups (e.g., even columns in one group, odd columns in another) while maintaining relatively simple decoding logic within each group. The segmentation approach improves multi-dimensional data processing capability without requiring a complete redesign of the decoding circuit.
Solution Approach 2:
The column group selection signal acts as an intermediary between the column address and the actual column selection. Instead of directly decoding the full column address to select individual columns, the system first selects a column group using the intermediary selection signal, then decodes the column address within that group. This intermediary mechanism enables flexible non-consecutive access patterns while keeping the decoding circuit relatively simple, as each decoder only needs to handle a subset of columns rather than the entire column space.
Data Source
AI summary
A memory device includes a memory cell array, a row decoder, a multi-column decoder, a gating circuit, and an input/output data driving circuit. The memory cell array includes a plurality of memory cells arranged to form a plurality of rows and a plurality of columns. The row decoder generates a row selection signal based on a row address to select a target row from the rows. The multi-column decoder generates a multi-column selection signal based on a column address and column selection information to select a plurality of target columns from columns included in the target row at a time. The gating circuit selects the target columns at a time based on the multi-column selection signal. The input/output data driving circuit writes input data to the target columns at a time or outputs data stored in the target columns at a time as output data through the gating circuit based on the multi-column selection signal and a data mask signal. Column addresses corresponding to the target columns included in the target row are not consecutive.