Multi-column Interleaved DIMM Placement for High Density PCB Routing
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Solution Overview
Problem
The challenge in data centers is to efficiently scale server resources, particularly in scale-up servers, where adding more memory channels is hindered by space constraints on printed circuit boards, especially in smaller form factors, leading to difficulties in accommodating additional dual in-line memory modules (DIMMs) without increasing board size or reducing memory speed.
Innovation Solution
A multi-column interleaved DIMM placement and routing topology is implemented, where DIMM sockets are arranged in multiple columns across both sides of CPU sockets, allowing for increased memory density by interleaving DIMMs from different CPU groups, thereby optimizing PCB space and meeting design constraints for higher memory bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more memory channels are added to increase server memory capacity, then memory bandwidth and capacity are improved, but PCB space availability deteriorates due to space constraints on the printed circuit board
Solution Approach 1:
The patent utilizes both sides of the PCB to place DIMM sockets, transitioning from a single-sided layout to a dual-sided layout. This dimensional change allows memory sockets to be distributed across both faces of the board, effectively doubling the available space for memory modules without increasing the PCB footprint.
Solution Approach 2:
The patent divides the memory architecture into multiple columns (first column, second column, third column) distributed across both sides of the PCB. Each column is associated with specific CPU sockets and can be independently configured. This segmentation allows for flexible memory distribution and enables higher memory capacity by organizing sockets in a structured multi-column layout.
2Quantity of substance
If DIMM sockets are arranged in multiple columns across both sides of CPU sockets to increase memory density, then memory bandwidth is improved, but routing complexity worsens due to increased trace length and signal integrity challenges
Solution Approach 1:
The memory system is segmented into multiple independent columns, each with its own dedicated routing paths to specific CPU sockets. This segmentation allows for modular routing design where each column can be routed independently, simplifying the overall routing complexity despite the increased number of sockets. The interleaved column arrangement enables balanced signal distribution across the PCB.
Solution Approach 2:
By distributing columns across both sides of the PCB, the routing paths are optimized to minimize trace lengths. The multi-column layout on dual sides allows for shorter, more direct signal paths compared to concentrating all memory sockets on a single side, thereby reducing routing complexity and improving signal integrity.
3Quantity of substance
If the PCB size is increased to accommodate more DIMM sockets, then memory capacity is improved, but form factor constraints worsen due to half-width processor blade limitations
Solution Approach 1:
The patent exploits the third dimension by utilizing both sides of the PCB for socket placement. Instead of extending the PCB length to accommodate more sockets on a single side, the design wraps the socket arrangement around to the opposite side of the board. This approach maintains the half-width form factor while significantly increasing memory capacity through dual-sided socket distribution.
Solution Approach 2:
The patent combines multiple columns of memory sockets across both sides of the PCB into a unified memory architecture. The first column, second column, and third column are merged into a cohesive system that shares common control and data buses, allowing the PCB to support high memory capacity without requiring increased physical dimensions.
Data Source
AI summary
In one embodiment, a printed circuit board (PCB) has a first central processing unit (CPU) socket and a second CPU socket substantially in line with the first CPU socket, and also has a first plurality of dual in-line memory module (DIMM) sockets interconnected with the first CPU socket and a second plurality of DIMM sockets interconnected with the second CPU socket (in a direction parallel to the first plurality of DIMM sockets). The first plurality of DIMM sockets are arranged on the PCB in at least a first column and a second column of DIMM sockets, and the second plurality of DIMM sockets are arranged on the PCB in at least the second column and a third column of DIMM sockets, such that the second column of DIMM sockets contains interleaved DIMM sockets from each of the first plurality of DIMM sockets and the second plurality of DIMM sockets.