Multi-Comparator Circuit for Speed-Accuracy Switching
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Solution Overview
Problem
Comparators in integrated circuits face a challenge in balancing speed and accuracy, as improving accuracy through gain stages or auto-zeroing increases propagation delay, making it difficult to determine when to use fast but less accurate comparators versus more accurate but slower ones, especially in applications like SAR ADCs where bit trials require varying levels of speed and accuracy.
Innovation Solution
A variable speed comparator circuit comprising three comparators with different accuracy and speed characteristics, where the logic circuit determines the output based on the equivalence of the second and third comparators' outputs, using the faster but less accurate comparators for larger input differences and the slower but more accurate comparator for smaller differences, thereby optimizing speed and accuracy based on input offset.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If gain stages or auto-zeroing are used to improve comparator accuracy, then measurement precision is improved, but propagation delay increases making the comparator slower
Solution Approach 1:
The comparator system is divided into multiple independent comparator circuits, each with different accuracy-speed characteristics. Instead of using a single comparator with gain stages or auto-zeroing that would be slow, the system segments the comparison function across multiple comparators with varying precision levels, allowing fast comparisons to proceed without the delay penalties of accuracy-enhancing techniques.
Solution Approach 2:
The system changes the accuracy parameter of different comparator circuits to create a spectrum of speed-accuracy tradeoffs. By configuring comparators with different gain stages and auto-zeroing characteristics, the system creates multiple operating points where each comparator has optimized parameters for its intended use case, resolving the contradiction by offering parameter variation rather than a single fixed design.
2Device complexity
If a single comparator is used for all bit trials, then device complexity is reduced, but productivity decreases due to inability to optimize speed for different comparison needs
Solution Approach 1:
The system dynamically selects which comparator circuit to use based on the specific bit trial requirements. Rather than statically configuring a single comparator or permanently using multiple comparators for all operations, the system adaptively chooses the appropriate comparator circuit for each comparison task, optimizing productivity while managing complexity through controlled dynamic behavior.
Solution Approach 2:
Multiple comparator circuits are designed to perform the same basic comparison function but with different performance characteristics. This multi-functionality allows the system to handle various bit trial scenarios with appropriately optimized comparators, improving overall productivity while maintaining a unified approach to the comparison task across different operational contexts.
Data Source
AI summary
Various examples are directed to a variable speed comparator circuit comprising a first comparator, a second comparator, and a third comparator and a logic circuit. The first comparator may be configured to generate a first comparator output using a first input and a second input. The second comparator may be configured to generate a second comparator output using the first input and the second input. The third comparator may be configured to generate a third comparator output using the first input and the second input. A propagation delay of the second comparator may be less than a propagation delay of the first comparator. Also, a propagation delay of the third comparator may be less than the propagation delay of the second comparator. The second comparator may have an input offset relative to the third comparator. The logic circuit may be configured to determine that the second comparator output and the third comparator output are not equivalent and set a comparator circuit output to the first comparator output.