Multi-Composition Gate Dielectric Transistors
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Solution Overview
Problem
Integration schemes for replacement gate field effect transistors often damage silicon-oxide-based dielectric material portions during etch processes, making it challenging to use multiple types of gate dielectrics without compromising their reliability.
Innovation Solution
A method involving the formation of a stack comprising a silicon-based dielectric layer, a high-k material layer, and a metallic nitride layer on a semiconductor substrate, where the stack is patterned to protect certain regions, allowing for the deposition of semiconductor material layers and subsequent formation of gate structures with different dielectric compositions, including planar and U-shaped high-k gate dielectrics, to create reliable field effect transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If replacement gate field effect transistors are integrated with high-k gate dielectrics, then device reliability is improved, but silicon-oxide-based dielectric material portions are damaged by etch processes
Solution Approach 1:
The gate dielectric structure is segmented into multiple regions: a first region containing a silicon-oxide-based dielectric layer protected by a first mask, and a second region containing a high-k dielectric layer. This segmentation allows different dielectric materials to coexist without mutual interference during etch processes, protecting the silicon-oxide-based dielectric while enabling high-k dielectric integration for improved device reliability.
Solution Approach 2:
A first mask layer is introduced as an intermediary protective element during the formation of the gate dielectric structure. This mask selectively protects the silicon-oxide-based dielectric layer in the first region from damaging etch processes while allowing the high-k dielectric layer to be formed in the second region, thereby preventing harm to the silicon-oxide-based dielectric material portions.
2Adaptability or versatility
If multiple types of gate dielectrics are used on the same substrate, then device functionality is enhanced, but process complexity increases
Solution Approach 1:
Different dielectric materials are applied to different regions of the substrate according to specific functional requirements. The first region receives a silicon-oxide-based dielectric layer suitable for certain transistor types, while the second region receives a high-k dielectric layer for other transistor types. This local quality approach enhances device functionality by providing tailored dielectric properties in different areas while managing process complexity through region-specific processing.
Solution Approach 2:
The gate dielectric formation process is designed to serve multiple functions simultaneously: it forms different dielectric types for different transistor types on the same substrate, provides selective protection during etching, and enables subsequent replacement gate formation. The first mask layer and stacked structure serve multiple purposes in the overall fabrication sequence, reducing the need for separate processing steps for each dielectric type.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the use of multiple gate dielectrics with different thicknesses without damaging the silicon-oxide-based dielectric material, enhancing the integrity and reliability of semiconductor structures by protecting the dielectric layers from etch processes and allowing for the formation of effective gate electrodes.
Implementation Method 1
The second gate structure is replaced with a replacement gate structure including a chemical oxide portion
Implementation Method 2
A stack of a silicon-based dielectric material layer, a high dielectric constant (high-k) material layer, and a metallic nitride layer is formed over a surface of a semiconductor substrate
Implementation Method 3
A stack of a silicon-based dielectric material layer, a high dielectric constant (high-k) material layer, and a metallic nitride layer is formed over a surface of a semiconductor substrate
Data Source
AI summary
A first gate structure and a second gate structure are formed over a semiconductor material layer. The first gate structure includes a planar silicon-based gate dielectric, a planar high-k gate dielectric, a metallic nitride portion, and a first semiconductor material portion, and the second gate structure includes a silicon-based dielectric material portion and a second semiconductor material portion. After formation of gate spacers and a planarization dielectric layer, the second gate structure is replaced with a transient gate structure including a chemical oxide portion and a second high-k gate dielectric. A work-function metal layer and a conductive material portion can be formed in each gate electrode by replacement of semiconductor material portions. A gate electrode includes the planar silicon-based gate dielectric, the planar high-k gate dielectric, and a U-shaped high-k gate dielectric, and another gate electrode includes the chemical oxide portion and another U-shaped high-k gate dielectric.