Multi-constraint Qubit Allocation for Quantum Apparatus
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Solution Overview
Problem
Current qubit allocation methods for near-fault-tolerant quantum computing (FTQC) face challenges in efficiently addressing hardware topology constraints, frequency group limitations, and latency issues, leading to increased errors and circuit execution time.
Innovation Solution
A multi-constraint qubit allocation (MCQA) method that considers hardware topology, frequency groups, primitive gate sets, and latency, using frequency-aware graph matching for initial mapping and dynamic scheduling for main mapping to achieve maximum parallelism and reduce additional gates and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional gates are added to satisfy connectivity constraints in main mapping, then connectivity is improved, but circuit depth and error rate increase
Solution Approach 1:
The patent performs initial mapping before main mapping to pre-establish optimal qubit assignments that satisfy connectivity constraints. By determining the mapping in advance rather than adding gates during execution, the circuit depth increase is minimized while still achieving connectivity satisfaction.
Solution Approach 2:
The patent introduces an initial mapping phase as an intermediary step between circuit design and main mapping. This intermediary process generates a mapping configuration that mediates between the original circuit requirements and hardware connectivity constraints, reducing the need for additional gates in the main mapping phase.
2Adaptability or versatility
If qubit mapping is optimized for connectivity, then hardware compatibility is improved, but latency and execution time increase
Solution Approach 1:
The patent performs preliminary mapping optimization that simultaneously considers both connectivity requirements and latency implications. By pre-calculating the optimal mapping configuration before main mapping, the system achieves hardware compatibility while minimizing the impact on execution time.
Solution Approach 2:
The patent adjusts mapping parameters and configuration variables to find optimal solutions that balance connectivity satisfaction with latency reduction. By changing mapping parameters strategically, the system achieves hardware compatibility without excessive latency penalties.
3Manufacturing precision
If comprehensive hardware constraints are considered in mapping, then mapping accuracy is improved, but computational complexity increases
Solution Approach 1:
The patent segments the qubit mapping process into distinct phases: initial mapping and main mapping. Each phase handles specific constraints separately, which reduces the computational complexity of each individual phase while maintaining overall mapping accuracy through the cumulative effect of both phases.
Solution Approach 2:
The patent performs preliminary processing of hardware constraints and circuit requirements before executing the main mapping algorithm. By pre-organizing and filtering constraint information, the system reduces the computational burden on the main mapping phase while ensuring all constraints are accurately satisfied.
Data Source
AI summary
Disclosed is a multi-constraint qubit allocation method and a quantum apparatus using the same. The method comprises generating an interaction graph representing a quantum circuit on the basis of the number of two-qubit gates, determining edge weights between connected nodes in the interaction graph by introducing a fitting coefficient for a decay effect, searching for an isomorphic part, layout graph, between target hardware and the interaction graph by graph matching, and performing frequency matching for a layout graph by searching for frequency allocated to each location of qubits by limiting unidirectional movement on each of an x-axis and a y-axis of a hardware plane of the target hardware to a range from −1 to +1.